ENHANCE: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models
Überblick
Key Facts
- Grant Number:
- 01|H11004A
- Art des Projektes:
- Sonstiger Zweck
- Laufzeit:
- 04/2011 - 12/2013
- Gefördert durch:
- Bundesministerium für Forschung, Technologie und Raumfahrt (BMFTR)
Detailinformationen
Publikationen
Performance-centric scheduling with task migration for a heterogeneous compute node in the data center
A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.
Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing
T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.
Parallel Macro Pipelining on the Intel SCC Many-Core Computer
T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.
Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux
T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.
Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend
Alle Publikationen anzeigen
B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.
Gefördert durch:
