Die Werkzeugdemonstration des QEMU Timing Analyzers (QTA) stellt eine Erweiterung des quelloffenen CPU Emulators QEMU zur Simulation von Softwareprogrammen und deren Worst-Case Zeitverhaltens vor, das durch eine statische Zeitanalyse vorher aus dem Softwareprogramm extrahiert wurde. Der Ablauf der Analyse gliedert sich in mehrere Schritte: Zunächst wird für das zu simulierende Binärprogramm eine WCET-Analyse mit aiT durchgeführt. Im Preprocessing des aiT-Reports wird daraufhin ein WCET-annotierter Kontrollflussgraph erzeugt. Dabei entsprechen die Knoten im Kontrollflussgraph den aiT-Blöcken und die Kanten dem jeweiligen Worst-Case-Zeitverbrauch, um das Programm im aktuellen Ausführungskontext vom Quell- bis zum Zielblock laufen zu lassen. Nach dem Preprocessing werden Binärprogramm und der zuvor erzeugte, zeitannotierte Kontrollflussgraph von QEMU geladen und gemeinsam simuliert. Die Implementierung des QTA basiert auf der Standard TGI Plugin API (Tiny Code Generator Plugin API), die seit Ende 2019 mit QEMU V4.2 verfügbar ist. Dieses API erlaubt die Entwicklung von versionsunabhängigen QEMU-Erweiterungen. Die QEMU-QTA-Erweiterung wird zum Zeitpunkt der Werkzeugdemonstration inklusive des ait2qta-Preprozessors unter github.com im Quellcode frei verfügbar sein. Die Demonstration geht von einer existierenden aiT-Analyse eines für TriCore© kompilierten binären Softwareprograms aus, erläutert das Kontrollflusszwischenformat und zeigt die zeitannotierte Simulation der Software.

We present a monolithically integrated electronic-photonic Mach-Zehnder modulator with a linear, segmented driver on the same silicon substrate. As metric for the modulation efficiency, the external V$\pi$ is hereby reduced to only 420 mV.

We present the optical generation of a 300 Gbaud PRBS-7 data signal based on time-division multiplexing of Nyquist sinc-pulse sequences. The employed electronic and photonic components need only one-third of the final bandwidth.

We demonstrate a photonic-electronic analog-to-digital converter (ADC) offering a record-high acquisition bandwidth of 320 GHz. The system combines a high-speed electro-optic modulator with a Kerr comb for spectrally sliced coherent detection and is used for digitizing ultra-broadband data signals.

The circuit design and measurement results of a mixed-signal receiver baseband circuit for a wireless high data rate communication system are presented. The circuit design of the two most important system blocks of the sliced receiver baseband architecture, namely the broadband, programmable code-generator circuit, and the integrate and dump correlator circuit are explained. Using parallel sequence spread spectrum (PSSS) with PAM-4 modulated data, a net data rate of 2.22 Gbps is demonstrated with a single receiver baseband slice circuit working with a chip rate of 20 Gcps. A total of 15 slices are required to recover all 15 parallelly transmitted symbols resulting in the net data rate of 33.33 Gbps. This is the first reported implementation of a mixed-signal PSSS baseband circuit.

An m-sequence radar with a high chip rate of 20 Gcps is presented that makes use of the large bandwidth available in the V-band (40-75 GHz) or at 240 GHz to reduce the detection resolution to 7.5 mm. Measurement results of a mixed-signal radar receiver baseband (BB) integrated circuit designed using 130 nm SiGe BiCMOS technology are presented along with a novel radar ranging concept for the mixed-signal radar BB.

We demonstrate for the first time, to the best of our knowledge, reconfigurable and real-time orthogonal time-domain demultiplexing of coherent multilevel Nyquist signals in silicon photonics. No external pulse source is needed and frequencytime coherence is used to sample the incoming Nyquist OTDM signal with orthogonal sinc-shaped Nyquist pulse sequences using Mach-Zehnder modulators. All the parameters such as bandwidth and channel selection are completely tunable in the electrical domain. The feasibility of this scheme is demonstrated through a demultiplexing experiment over the entire C-band (1530 nm - 1550 nm), employing 24 Gbaud Nyquist QAM signals due to experimental constraints on the transmitter side. However, the silicon Mach-Zehnder modulator with a 3-dB bandwidth of only 16 GHz can demultiplex Nyquist pulses of 90 GHz optical bandwidth suggesting a possibility to reach symbol rates up to 90 GBd in an integrated Nyquist transceiver.

This paper presents a technique to extend the frequency acquisition range for bang-bang phase-detector-based clock and data recovery (CDR) circuits without an additional frequency acquisition loop or lock detection circuit. The per-manent modulation of the offset current in the CDR's integral branch enhances the acquisition range by nearly 4 times, covering the entire tuning range of the voltage controlled oscillator. The increase in power dissipation and the chip area are negligible. This technique was implemented and measured in a 28 Gbps NRZ bang-bang CDR chip to confirm the working principle. In addition to the increased acquisition range, the CDR also surpasses jitter related specifications from the OIF CEI-28G-VSR standard.

Fault coverage analysis and fault simulation are well-established methods for the qualification of test vectors in hardware design. However, their role in virtual prototyping and the correlation to later steps in the design process need further investigation. We introduce a metric for RISC-V instruction and register coverage for binary software. The metric measures if RISC-V instruction types are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied by the means of a virtual prototype which is based on an abstract instruction and register model with direct correspondence to their bit level representation. In this context, we analyzed three different openly available test suites: the RISC-V architectural testing framework, the RISC-V unit tests, and programs which are automatically generated by the RISC-V Torture test generator. We discuss their tradeoffs and show that by combining them to a unified test suite we can arrive at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage.

Novel analog-to-digital converter (ADC) architectures are motivated by the demand for rising sampling rates and effective number of bits (ENOB). The main limitation on ENOB in purely electrical ADCs lies in the relatively high jitter of oscillators, in the order of a few tens of fs for state-of-the-art components. When compared to the extremely low jitter obtained with best-in-class Ti:sapphire mode-locked lasers (MLL), in the attosecond range, it is apparent that a mixed electrical-optical architecture could significantly improve the converters' ENOB. We model and analyze the ENOB limitations arising from optical sources in optically enabled, spectrally sliced ADCs, after discussing the system architecture and implementation details. The phase noise of the optical carrier, serving for electro-optic signal transduction, is shown not to propagate to the reconstructed digitized signal and therefore not to represent a fundamental limit. The optical phase noise of the MLL used to generate reference tones for individual slices also does not fundamentally impact the converted signal, so long as it remains correlated among all the comb lines. On the other hand, the timing jitter of the MLL, as also reflected in its RF linewidth, is fundamentally limiting the ADC performance, since it is directly mapped as jitter to the converted signal. The hybrid nature of a photonically enabled, spectrally sliced ADC implies the utilization of a number of reduced bandwidth electrical ADCs to convert parallel slices, resulting in the propagation of jitter from the electrical oscillator supplying their clock. Due to the reduced sampling rate of the electrical ADCs, as compared to the overall system, the overall noise performance of the presented architecture is substantially improved with respect to a fully electrical ADC.

This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding 60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375 mW.

In this paper we propose a novel low-power receiver architecture which uses a direct-detection receiver in combination with a 2.44 GHz 13 bit Barker Code SAW correlator for improvement of co-channel interference. Furthermore, to improve receiver sensitivity, a narrowband baseband correlator which uses pulse position modulation (PPM) is proposed. The receiver can be used as a Wake-up Receiver (WuRx) in Wireless Sensor Networks (WSN) to minimize the power dissipation and provide asynchronous and on-demand data communication. We present a rigorous analysis of the receiver. It shows that the RF front-end (SAW correlator and envelope detector) alone suffers from poor sensitivity due to the high baseband bandwidth and the absence of an RF low noise amplifier. However, by adding the narrowband correlator with an innovative Pulse Position Modulation (PPM) scheme, the overall sensitivity of the receiver reaches -63.1 dB with an improvement of 17.7 dB due to the use of the narrowband correlator that reduces the baseband bandwidth from 50 to 0.84 MHz. By scaling the narrowband correlator bandwidth further down, the receiver sensitivity can be further improved.

In this paper we present a new system concept for an optoelectronic wireless phased array system. Like in a conventional phased array system with optical carrier distribution, optical fibers are used to distribute the carrier from the basestation to the wireless frontends. However in contrast to prior concepts, we propose to use an optical IQ return path from the wireless frontends back to the basestation. Furthermore, we reuse the optical carrier signal for the IQ return path which allows to avoid local oscillator lasers in the wireless frontends and reduces the hardware effort significantly. The system concept allows to integrate all components of an optoelectronic wireless frontend in a single chip using silicon photonics technology.

Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.

A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a 0.25 μm monolithic photonic BiCMOS technology. The core chip area is 0.51 mm 2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies.

Low-power receivers use direct-detection receiver architecture for its design simplicity and its low power dissipation. However, the direct-detection based receivers suffer from co-channel interference which significantly degrades the communication reliability. Co-channel interference robustness can be improved by using a BPSK Barker code modulated Surface Acoustic Wave (SAW) correlator as a prior stage to the RF direct detection circuit. This paper reports in details the design, fabrication and measurements of a 2.45 GHz SAW correlator with 13 bits length Barker code. The device is fabricated on Lithium Niobate LiNbO3 substrate and it is composed of an input non-coded Inter Digital Transducers (IDT), a Piezoelectric substrate and an output coded IDT. The device wavelength λ is set to 1.6 μm, considering a phase velocity of the wave equal to 3970 m.s-1. Several configurations of the device were designed and fabricated, particularly varying the aperture and the non-coded IDT length to find out the optimal device configuration. All devices were found to operate with Insertion Loss (IL) ranging from 12 to 15 dB at 2.45 GHz with a tip probing measurement setup, while a packaged sample has an IL of 12.45 dB at 2.44 GHz mounted on a PCB with external 50 Ω LC matching network. Additionally, time-domain measurement for the packaged device shows that the output has a correlation peak with a peak-to-side-lobe (PSL) ratio of 4:1 for a -0.5 dBm input BPSK Barker code signal.

Recently it has been demonstrated that an optoelectronic phase-locked loop (OEPLL) using a mode-locked laser as a reference oscillator achieves significantly lower phase noise than conventional electronic frequency synthesizers. In this paper a concept for an OEPLL-based frequency synthesizer is presented and it is investigated how it can be used as a local oscillator (LO) for THz transceivers in order to improve the signal quality in THz wireless communications. The concept of the OEPLL is presented and it's measured phase noise is compared to the phase noise of a laboratory-grade electronic frequency synthesizer. The measured phase noise spectra of both synthesizers at 10 GHz are then used to model LO phase noise at 320 GHz. Based on models of generic zero-IF transmit and receive frontends, THz signals with different modulation formats and Baud rates are simulated at system level using the modeled LO phase noise for the two LO approaches. Finally, the results are compared.

This paper presents an ultra-wideband and ultra-low noise frequency synthesizer using a mode-locked laser as its reference. The frequency synthesizer can lock in the frequency range from 2 GHz to 20 GHz on any harmonic of a mode-locked laser optical pulse train. The integrated rms-jitter (1 kHz-100 MHz) of the synthesizer is less than 5 fs in the frequency range from 4 GHz to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband phase locked loop achieving sub-10 fs rms-jitter for offset frequencies larger than 1 kHz.

This paper presents a broadband sampler IC using a current-mode integrated-and-hold-circuit (IHC) as sampling circuit. The sampler IC exhibits 1dB large-signal bandwidth of 70 GHz and excellent signal integrity on hold-mode. With a sampling rate of 5 GS/s, it achieves effective number of bits (ENOB) of 6 bit at 9.9 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP.

Using direct-detection architecture in Radio Frequency (RF) receivers allows for ultra-low power dissipation and is often used in Wake-Up receivers. Unfortunately direct-detection receivers suffer from high sensitivity to co-channel interference which reduces the communication performance and reliability. In this paper, it is shown that co-channel interference robustness of direct-detection receivers is improved by using Binary Phase Shift Keying (BPSK) Barker code modulated Surface Acoustic Wave (SAW) correlator as a prior stage to the RF envelope detector. Replacing the band select filter with SAW correlator does not result in higher receiver hardware cost. In our receiver, the SAW correlator functions as a passive signal processor, providing gain for a BPSK Barker code modulated signal, while suppressing in-band interferers. This improves the co-channel interference robustness of the direct-detection receiver while preserving its advantage of power efficiency. The concept is verified by means of a direct-detection receiver with discrete components on an RF PCB including an SAW Barker Code correlator at a center frequency of 2.44 GHz fabricated on Lithium Niobate substrate. Measurements with WiFi signals demonstrate that the interference robustness is improved by more than 10 dB compared to a conventional direct-detection receiver.

This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits a record 3dB small-signal bandwidth of 70 GHz. With the high sampling rate of 40 GS/s, it achieves an effective number of bits (ENOB) of 7.5 bit at 1 GHz input frequency and an ENOB of >5 bit up to 15 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 110 mA from a -4 V supply voltage, dissipating 440 mW.

We overview the 3-year Meteracom project which will provide traceability to the SI for THz communication measurement parameters. The key objectives are to develop new metrological methods to characterize the measurement systems, system components and propagation channels. The final objective is to develop metrology for functionality and signal integrity of THz communication systems; particularly device discovery and beam tracking, determination of physical layer parameters for digital transmission and real-time performance evaluation.

Optical sampling of pseudo random microwave signals with sinc-shaped Nyquist pulse sequences has been demonstrated in an integrated silicon photonics platform. An electronic-photonic, co-integrated depletion type silicon intensity modulator with high extinction ratio has been used to sample the microwave signal with a sampling rate, which corresponds to three times its RF bandwidth. Thus, a sampling rate of 21 GSa/s is achieved with a 7 GHz modulator, with 3 dBm of differential input power.

Targeting the feasible application of microwave RFID systems with MIMO reader technology for tracking small objects in multipath fading conditions, we present a fully integrated Analog Front-End (AFE) designed and fabricated in a standard 65-nm CMOS technology for low power passive RFID tags in the 5.8 GHz ISM band. A differential drive power scavenging unit is dimensioned to provide a 1.2 V rectified voltage resulting in a 1 V regulated voltage for the AFE while supplying a 50 μW load. Transistors with standard threshold voltage (V th ) have been used for implementation. Measurements of the fabricated circuits show a maximum Power Conversion Efficiency (PCE) of 71.8% at -12.5 dBm, and an input quality factor (Q-factor) of approximately 10.

Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.

We present a complete Visible Light Communication (VLC) system for experimental Vehicular VLC (V-VLC) research activities. Visible light is becoming an important technology complementing existing Radio Frequency (RF) technologies such as Cellular V2X (C-V2X) and Dedicated Short Range Communication (DSRC). In this scope, first works helped introducing new simulation models to explore V-VLC capabilities, technologies, and algorithms. Yet, experimental prototypes are still in an early phase. We aim bridging this gap with our system, which integrates a custom-made driver hardware, commercial vehicle light modules, and an Open Source signal processing implementation in GNU Radio, which explicitly offers rapid prototyping. Our system supports OFDM with a variety of Modulation and Coding Schemes (MCS) and is compliant to IEEE 802.11; this is in line with the upcoming IEEE 802.11 LC standard as well. In an extensive series of experiments, we assessed the communication performance by looking at realistic inter vehicle distances. Our results clearly show that our system supports even higher order MCS with very low error rates over long distances.

In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann.

An octave-band voltage-controlled oscillator is phase-locked on the envelope of the pulse train from a mode-locked laser. The locking scheme employs a balanced Mach-Zehnder modulator with two photodiodes as a phase detector. The phase.locked loop has a loop bandwidth of approximately 1MHz and an in-band phase noise of approximately -135dBc/Hz at all frequencies. The integrated jitter from 1kHz to 100MHz is 21fs, 18.3fs and 13.8fs at 5.016GHz, 7.6GHz and 10.032GHz carrier frequencies, respectively. To the authors' knowledge, this is the best jitter performance reported for a PLL with MZM-based phase detection and the first reported PLL of this type featuring an octave-band frequency range.

In this poster, we present the first experimental results of our OFDM-based Vehicular VLC (V-VLC) prototype. Our Bit Error Rate (BER) measurements show that for lower Modulation and Coding Schemes (MCS), the performance of our hardware-setup roughly behaves the same as it does in simulation for AWGN channel. However, for higher order MCS with high PAPR, the BER performance gets degraded due to non-linear behavior of LEDs, and deviates further from AWGN performance as the MCS order is increased. The obtained results suggest that unlike RF-Communications, where the focus is usually towards linearity of the amplifiers, for V-VLC, linearity within the whole system is required to achieve optimal performance.

A 2nd transconductance subharmonic receiver for 245 GHz spectroscopy sensor applications has been proposed. The receiver consists of a 245 GHz on-chip folded dipole antenna, a CB (common base) LNA, a 2nd transconductance SHM (subharmonic mixer), and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in fT/fmax = 300/500 GHz SiGe:C BiCMOS technology. The receiver dissipates a low power of 288 mW. Integrated with the on-chip antenna, the receiver is measured on-chip with a conversion gain of 15 dB, a bandwidth of 15 GHz, and the chip will be utilized in PCB board design for gas spectroscopy sensor application.

In this paper, we present a monolithically integrated coherent receiver with on-chip grating couplers, 90° hybrid, photodiodes and transimpedance amplifiers. A transimpedance gain of 7.7 kΩ was achieved by the amplifiers. An opto-electrical 3 dB bandwidth of 34 GHz for in-phase and quadrature channel was measured. A real-time data transmission of 64 GBd-QPSK (128 Gb/s) for a single polarization was performed.

We present a transmitter circuit to drive a commercial Light Emitting Diode (LED)-based headlight for automotive Visible Light Communication (VLC). Based on the design of the presented transmitter (TX), we provide a design methodology for VLC TXs and make it available as Open Hardware. Furthermore, a complete wireless VLC link is built using the GNU Radio signal processing tool chain and demonstrated on an Universal Software Radio Peripheral (USRP). The Total Harmonic Distortion (THD) of the system is below 5% for a wide input voltage range and the 1 dB compression point (P1dB) is at 1.02V, which makes the circuit attractive for more advanced modulation formates like Orthogonal Frequency Division Multiplexing (OFDM) or Pulse-Amplitude Modulation (PAM).

The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. In our system design, we require a DAC (Digital to Analog converters) running at 1.67 G symbols/sec. The optimization of the bit resolution of this DAC will considerably reduce the hardware implementation efforts. In this work, we presented the analytical model for PSSS modulation and deduced a mathematical formula to calculate the number of discrete level amplitudes along with their probability distribution appearing at the output of the PSSS modulated signal. The analytical analysis assists in predicting the number of the quantization level of the DAC needed at the PSSS transmitter. The theoretical analysis shows that there are in total 225 discrete levels at the output of the PSSS encoder which leads to an 8-bit resolution of DAC. In this paper, we analyzed the variation of BER (Bit Error Rate) to the clipping of low probability amplitude levels and found that there is an only slight increase of the BER when we clip off the low probability amplitude levels. Thus, there is a tradeoff involved in a minor growth of BER concerning the reduction of the DAC bit resolution. Finally, we can reduce the DAC bit resolution from 8 bits to 7 bits and thus simplify the hardware implementation efforts of DAC operating at 1.67 Gbps.

A complete system analysis for an integrated passive RFID transponder designed at 5.8 GHz range is presented, and a comprehensive set of design concerns for the rectifier circuit as the core of the harvesting block is also discussed. The system analysis is complemented by transistor-level design and simulation of harvesting circuits in a commercial 65 nm CMOS technology. A differential drive rectifier (DDR) has been selected as the most efficient harvesting topology for microwave frequency applications, which works at very low input power levels. The circuit was designed and simulated including chip layout parasitics and antenna matching circuitry. Considering the power budget of the tag chip, a power conversion efficiency of roughly 68.4% is achieved in simulation for an input RF power of around -11.26dBm.

This paper demonstrates system level analysis of an energy efficient Radio Frequency (RF) receiver. The receiver is based on a Surface Acoustic Wave (SAW) correlator which is used for highly linear demodulation and interferer suppression in conjunction with envelope detection for ultra-low power dissipation and hardware efficiency. The receiver is to be used in Wireless Sensor Networks (WSN) as a Wake-up Receiver (WuR) to reduce the network nodes power dissipation and provide asynchronous data communication. Low latency and high interference robustness makes this scheme interesting for industrial real-time applications. In this paper, the SAW correlator transfer function is derived, which functions as a Matched Filter (MF). Since the receiver uses envelope detection and based on the characteristic of the SAW, the receiver sensitivity is analyzed by means of a non-linear approach.

This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.

A monolithically integrated coherent receiver in silicon photonic technology is presented along with measurement results for constellation diagrams up to 64GBd and bandwidth of 34 GHz. To our knowledge this is the fastest single-chip coherent receiver.

This work describes a dielectric sensing system applying a 120 GHz electrical interferometer for contactless permittivity measurements. The applied IC was fabricated in a 130 nm SiGe process featuring an ft and fmax of 240 GHz and 330 GHz. The on-chip system contains a 120 GHz VCO with a tuning range of 7 GHz featuring a divide-by-64 circuit to enable external PLL operation. An important feature of the IC is high-precision and high-resolution phase shifting based on a slow-wave transmission lines approach with digital control. This allows for direct digital readout ability. The on chip power detector provides DC output signals giving the opportunity to record transfer functions of the interferometer. It enables sample emulation capability by phase shift inducement in the measurement as well as a reference transmission line. The motherboard of the system provides PLL stabilization for frequency sweeps. The proposed approach is capable of automated dielectric monitoring by phase compensation.

Wireless Sensor Networks (WSN) consist of large number of distributed sensors nodes which are able to sense, read and transmit physical measurements such as temperature, humidity and pressure over wireless communication links. WSN nodes are often powered by batteries or can use energy harvesting methods from environmental energy sources. One of the major challenges in the design of WSN nodes is the high level of power dissipation for sensing, processing and communication. Operating at low-power levels reduces maintenance effort for periodic battery replacement or can even provide unlimited operation by means of energy harvesting. Since the communication process is the most power hungry process, ultra-low-power wireless communication is an enabler for network applications such as cyber-physical systems, Internet-of-Things and Industry 4.0 etc. Our research is based on Wake-up Receivers (WuR) architectures. Each of the WSN nodes contains a WuR which is always-on, listening for a wake-up signal from other nodes or the base station, and activating the node only when a wake-up signal is detected. By this scheme the communication with the base station becomes asynchronous, real-time and on-demand. Due to the centrally-coordinated, collision-free communication such WSNs can be scaled to very large node numbers. Designing always-on WuR at ultra-low-power dissipation levels makes the WSN nodes very energy efficient because they are only activated when a wake-up-signal is received. Additionally, the WuR must be robust to noise and co-channel interference in order to operate safely in parallel to other wireless systems. We investigate a novel radio architecture for the WuR using Linear Frequency Modulation (LFM) and passive analog signal processing by means of a Surface Acoustic Wave (SAW) correlator. The base station sends the required WSN node ID using LFM signal at 2.4 GHz. The node ID is encoded as chirp up or chirp down signal with chirping bandwidth of 80MHz. On the receiver side, the SAW chirp correlator demodulates the received LFM signal while suppressing other wireless signals. In order to achieve proper demodulation and high Signal-to-Noise Ratio (SNR), the SAW correlator is designed to behave like a Matched Filter (MF) which boosts up the SNR. After that the signal is amplified/detected by baseband amplifier stage, it is compared with the unique ID of the node, and the node's Wake up signal is asserted accordingly. Since the SAW correlator operates completely passive, the WuR can be implemented in a very energy-efficient way, without the need to use power hungry device such as Low Noise Amplifiers (LNA) or down conversion Local Oscillators (LO)

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that is well suited for mixed-signal transceiver implementation for high data rate wireless communication systems. Mixed signal baseband realization allows for easier implementation of the channel equalization function and eliminates the need for high speed data converters. System design and architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area. An ultra-broadband analog correlator consisting of a four-quadrant multiplier and a fast resettable integrator using only NPN transistors was designed, fabricated, and measured. The correlator circuit is the core component of the receiver baseband. To the best knowledge of the authors, it is the fastest correlator circuit published so far.

In this paper we present theoretical, simulated and measured data for a reader to tag communication RFID system at 5.8 GHz. First a theoretical link budget analysis for a reader to tag architecture is shown for a wireless industrial application at 1m distance. This includes a power budget of the passively powered transponder. The received power level of the backscattered data for the theoretical link budget is -52:5 dBm. For the first setup slot antennas are developed and measured in the anechoic chamber. The measured gain is 4.0 dB. The power of the backscatter data in setup 1 is -74:8 dBm. This corresponds to the theoretical link budget since, all losses such as cable or lower antenna gain are taken into account. Setup 2 is upgraded on the reader side with horn antennas. At 5.8 GHz, the gain reaches the value of 10.8 dB. The second setup shows improvement in the receiving backscattered power to a value of -62:4 dBm. Furthermore, as a solution to detect those transponders not presented in the main slope of the antenna, a steerable beam is introduced by means of a Rotman lens. On the topic of the passive transponder, different harvesting topologies at 5.8 GHz are investigated, and the efficiency simulation of the harvesting circuitry has been performed. The simulated efficiency of the implemented technique is 68 %.

This paper focuses on the design of a high efficiency cross-connected differential drive rectifier for next-generation passive RFID tags. To provide a realistic estimation of the transponders’power and efficiency requirements at 5.8 GHz, detailed link/power-budget analysis for various blocks of the tag chip is carried out. From link budget analysis realistic RF power levels are obtained and a rectifier with high conversion efficiency at low power levels is designed. Simulations based on a commercial 65nm CMOS technology investigate the suitability of the harvesting circuit for 5.8 GHz RFID tags.

This paper presents the design flow of using sampling technique for fault injection on sche- matic level. The parameters used in the docu- ment to calculate the likelihood could be modi- fied by using more realistic data from the fab. With the help of the fault simulator, the whole design flow of the fault effect simulation can be realized automatically.

Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.

Recently electronic-photonic integrated circuits (EPIC) technology platforms became available [1] which allow fabrication of very compact and fast monolithic receivers. However, although the cointegration of electronics and photonics on the same chip allows for novel circuit topologies which could help to improve circuit performance quite often transmitter and receiver circuit design is using more or less conventional approaches. We propose a novel architecture that effectively utilizes the benefits of the EPIC technology such as: very short interconnects between the photodiode and the amplifier, symmetrical and compact photodiode structure with low operating voltages. Our architecture shown in Fig. 1 features fully-differential input stage, automatic biasing of the photodiode, DC coupling between diode and transimpedance amplifier (TIA) and very small footprint.

This paper presents a four stage all-transmission-line 220 GHz differential LNA in SiGe BiCMOS technology. Cascode topology is chosen for each stage. The amplifier takes advantage of microstrip transmission lines to realize the inductive load, Marshand balun, input, output, and inter-stage matching of the LNA. The LNA has a gain of 21 dB at 224 GHz, a 3 dB bandwidth of more than 6 GHz. It has a supply voltage of 3V and power dissipation of 234 mW. The amplifier is intended for the use in communication, security scanning, imaging and remote sensing at 220 GHz.

The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.

Currently, all drone manufactures face the same problem: flight safety utility will become mandatory to obtain the legal admission for broad commercial use of drones. This means that on-board obstacle detection and collision avoidance is a must-have in order to overcome existing legal barriers and acceptance issues. Some of the currently available sensors are too large, too heavy, or can be poorly integrated into existing systems. During the exhibition a demonstration of a novel micro-sensor operating at 120 GHz will be given and participants will have the chance to experience the device first-hand.

An ultra-broadband analog correlator consisting of a four-quadrant multiplier and an ultra-fast resettable integrator using only NPN transistors was designed, fabricated, and measured. For the integrator, a cross-coupled transistor pair is used as a negative resistance generator. A novel ultra-fast reset circuit is implemented which allows to reset the integrator within very short time of 120 ps. The chip was fabricated using 130 nm SiGe BiCMOS technology with fT of 250 GHz and f max of 300 GHz. In the measurements carried out on printed circuit board, the correlator operated without noticeable performance degradation with inputs up to 33 Gbps which correspond to a bandwidth of more than 24 GHz. The correlator exhibits high linearity with output P1dB of more than 9.9 dBm (700 mV diff ) for both inputs. It dissipates 122.5 mW for the core circuit excluding the 50 Ω output driver. To the knowledge of the authors, the circuit represents the fastest analog correlator published so far. It can be used for spread spectrum communication, radar signal processing, and measurement applications.

In this paper a prototype of an ultra-compact continuous-wave (CW) and frequency-modulated continuous-wave (FMCW) radar system using a highly-integrated radar chip and in-package antennas will be presented. An introduction will be given on the concept of antenna integration for millimeter-wave radar and the advantages of such systems. The radar then will be described in its main components, a 122 GHz Integrated Circuit including in-package antennas as well as the acquisition and processing system realized using flexible printed circuit board (FLEX PCB) technology. Furthermore initial measurements of the radar system will be presented and explained.

Terahertz frequency band of 0.06 - 10 THz is especially interesting for ultra-high-speed wireless communication to achieve data rates of 100 Gbps or higher. To accommodate this demand, advanced terahertz signal processing techniques need to be investigated. Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that seems to be suited for being used for ultra-high speed wireless communication since the receiver architecture is especially simple and can be implemented almost completely in analog hardware. In this paper, a PSSS modulated signal at a chip rate of 20 Gcps with a spectral efficiency of (only) 1 bit/s/Hz is transmitted using a linearity limited 240 GHz wireless frontend. PSSS transceiver models are realized offline in MATLAB/Simulink. The PSSS transmitter generates the PSSS modulated symbols that are loaded onto an Arbitrary Waveform generator (AWG) and then transmitted using the available 240 GHz wireless frontend. A Digital Storage Oscilloscope (DSO) samples and stores the received signal. The PSSS receiver performs synchronization, channel estimation and demodulation. For a coded data rate of 20 Gbps, an eye opening of 40% and a BER of 5.4·10 -5 has been measured. These results are highly promising to achieve data rates of up to 100 Gbps with PSSS modulation using a RF-frontend having higher linear operating range and thus allowing increasing the bandwidth efficiency to 4 b/s/Hz.

The recent rapid development of silicon photonics technology has spurred the process of on-chip integration of all kinds of opto-electronic components. One of the most common components of such type is the opto-electrical receiver. The monolithic implementation of the receiver could potentially have lower power consumption, higher sensitivity and bandwidth due to very short diode to amplifier connection length, which has very low parasitic capacitance and series resistance. The SiGe photodiode itself is also very compact, thus lowering the junction capacitance and improving its bandwidth. Among the different optical communication systems, coherent transmission lately received a lot of attention due to the rising requirements of the optical link capacity, and it was shown that this particular approach could benefit greatly from the monolithic integration, since the major component required for the demodulation on the receiver side – 90° optical hybrid – could be implemented fully passive and directly on the same chip as the receiver itself, together with digital post-processing circuitry. Despite the initial complexity of the modulation scheme, advanced silicon photonics components like this optical hybrid could make coherent transmission attractive even for short-range optical links. I would like to present the actual designs, implementation and measurement results of 90° fully passive optical hybrids, implemented in the IHP SG25PIC (passive photonics IC) technology. One of the designs is based on 4x4 multimode interferometer (MMI). The other one is based on two separate 2x2 MMIs with additional delay element. The final designs didn’t require any additional tuning after fabrication and have shown sufficient precision and performance for a coherent system design. The results of this work were later used for the design of monolithic coherent receiver.

In this paper, a miniaturized 122 GHz ISM band FMCW radar is used to achieve micrometer accuracy. The radar consists of a SiGe single chip radar sensor and LCP off-chip antennas. The antennas are integrated in a QFN package. To increase the gain of the radar, an additional lens is used. A combined frequency and phase evaluation algorithm provides micrometer accuracy. The influence of the lens phase center on the beat frequency phase and hence, the overall accuracy is shown. Furthermore, accuracy limitations of the radar system over larger measurement distances are investigated. Accuracies of 200 μm and 2 μm are achieved over a distance of 1.9 m and 5 mm, respectively.

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology which is gaining interest for both wireless and wired multi-gigabit communication systems. PSSS is well suited for mixed signal transceiver implementation including channel equalization and allows for a reduction in power dissipation by avoiding high speed data converters. The architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area.

Parallel Sequence Spread Spectrum (PSSS) is a physical layer baseband technology wherein parallel data streams are transmitted simultaneously by spreading them using orthogonal codes. PSSS was selected for the wireless sensor network standard IEEE802.15.4-2006 to increase data rate and improve performance in fading channels for frequency bands below 1 GHz. Since then it has gained interest for both wireless and wired communication links.