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Der Campus im Frühling. Bildinformationen anzeigen

Der Campus im Frühling.

Foto: Universität Paderborn, Kamil Glabica.

Dr. Hassan Ghasemzadeh Mohammadi

Kontakt
Publikationen
Dr. Hassan Ghasemzadeh Mohammadi

Technische Informatik

Postdoc

Telefon:
+49 5251 60-4344
Fax:
+49 5251 60-4250
Büro:
O3.134
Web:
Web(extern):
Besucher:
Pohlweg 51
33098 Paderborn

Liste im Research Information System öffnen

2020

A Hybrid Synthesis Methodology for Approximate Circuits

M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 1-6

Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches.


2019

Jump Search: A Fast Technique for the Synthesis of Approximate Circuits

L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Fourth Workshop on Approximate Computing (AxC 2019), 2019

State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.


CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation

L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability (2019), 99, pp. 277-290

Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.


Jump Search: A Fast Technique for the Synthesis of Approximate Circuits

L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19, ACM, 2019

State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution. In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.


2018

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation

L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, in: Third Workshop on Approximate Computing (AxC 2018), 2018

Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.


An MCTS-based Framework for Synthesis of Approximate Circuits

M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219-224

Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints.


2016

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

H. Ghasemzadeh Mohammadi, P. Gaillardon, J. Zhang, G.D. Micheli, E. Sanchez, M.S. Reorda, ACM Journal on Emerging Technologies in Computing Systems (2016), pp. 1-13

DOI


Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation

H. Ghasemzadeh Mohammadi, P. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2016), PP(99), pp. 1-1

DOI


2015

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

H. Ghasemzadeh Mohammadi, P. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology (2015), 14(6), pp. 1117-1126

DOI


On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors

H. Ghasemzadeh Mohammadi, P. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491-496

DOI


Fault modeling in controllable polarity silicon nanowire circuits

H. Ghasemzadeh Mohammadi, P. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition, EDA Consortium, 2015, pp. 453-458

DOI


2014

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

H. Ghasemzadeh Mohammadi, P. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163-168

DOI


2013

A fast TCAD-based methodology for Variation analysis of emerging nano-devices

H. Ghasemzadeh Mohammadi, P. Gaillardon, M. Yazdani, G. De Micheli, in: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013, pp. 83-88

DOI


Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study

P. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1-6

DOI


2010

Sub-threshold charge recovery circuits

M. Khatir, H. Ghasemzadeh Mohammadi, A. Ejlali, in: Computer Design (ICCD), 2010 IEEE International Conference on, IEEE, 2010, pp. 138-144

DOI


2009

Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors

H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on, IEEE, 2009, pp. 252-255

DOI


2008

A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic

H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444-447

DOI


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