- E-Mail:
- jan.dennis.reimer@uni-paderborn.de
- Telefon:
- +49 5251 60-3922
- Büroanschrift:
-
Pohlweg 47-49
33098 Paderborn - Raum:
- P1.6.08.4
Publikationen
Aktuelle Publikationen
Validating Statistical Delay Test Generation under Timing Variations via SAT-Based ATPG
H. Jafarzadeh, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: To Appear in: 27th IEEE Latin American Test Symposium (LATS2026), March 2026, Florianopolis, Brazil, 2026.
SAT-Based Validation of Statistical Delay Test Generation under Timing Variations
H. Jafarzadeh, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, SAT-Based Validation of Statistical Delay Test Generation under Timing Variations, Workshop: Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2026), Feb. 2026, 2026.
ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits
J.D. Reimer, S. Holst, S. Sadeghi-Kohan, H.-J. Wunderlich, S. Hellebrand, in: IEEE International Symposium of Electronics Design Automation (ISEDA’25), May 2025, Hong Kong, China, 2025.
Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression
A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
H. Jafarzadeh, F. Klemme, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024, IEEE, San Diego, CA, 2024.
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