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Der Campus im Frühling. Bildinformationen anzeigen

Der Campus im Frühling.

Foto: Universität Paderborn, Kamil Glabica.

Prof. Dr. Sybille Hellebrand

Kontakt
Vita
Publikationen
Prof. Dr. Sybille Hellebrand

Datentechnik (DATE)

Leiterin - Professorin

Telefon:
+49 5251 60-3002
Fax:
+49 5251 60-4227
Büro:
P1.6.08.1
Sprechzeiten:

nach Vereinbarung

Web:
Besucher:
Pohlweg 47-49
33098 Paderborn

Geschäftsstelle

Stellvertretende Institutsleiterin - Professorin

Telefon:
+49 5251 60-3002
Fax:
+49 5251 60-4221
Büro:
P1.6.08.1
Web:
Besucher:
Pohlweg 47-49
33098 Paderborn
Prof. Dr. Sybille Hellebrand
07/1986 - heute

Curriculum Vitae

Sybille Hellebrand received her Diploma in Mathematics from the University of Regensburg in 1986. In the same year she joined the Institute of Computer Design and Fault Tolerance at the University of Karlsruhe, where she finished her Ph.D. in Computer Science in 1991. From 1991 to 1992 she received a post-doctoral fellowship from the French government and continued her research work at the TIM3/IMAG Laboratory in Grenoble, France. In 1992 she joined the University of Siegen as a post-doctoral research and teaching assistant. For her habilitation project she received a Lise- Meitner Fellowship from the NRW government in 1995. Before she completed her habilitation in 1997 she spent several months as a guest researcher at Mentor Graphics Corporation in Portland, OR, USA. After her stay in the USA, Sybille Hellebrand moved to the University of Stuttgart as a permanent research and teaching assistant. In 1999 she was appointed full professor in Computer Science at the University of Innsbruck, Austria.

Since December 2004 she holds the chair for Computer Engineering at the Institute of Electrical Engineering and Information Technology at the University of Paderborn. Sybille Hellebrand is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the IEEE Test Technology Technical Council (TTTC). She has served on the program committees of many international conferences, and she was the General Chair of the IEEE European Test Symposium in 2014. She is an associate editor of the Journal of Electronic Testing – Theory and Applications (JETTA). From 2002 to 2009 she was a member of the editorial board of IEEE Transactions on Computer-Aided Design of Circuits and Systems. Her main research interests are in test, diagnosis, and fault tolerance of integrated circuits and systems.


Liste im Research Information System öffnen

2020

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study

A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020


Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects

S. Sadeghi-Kohan, S. Hellebrand, in: Proceedings IEEE VLSI Test Symposium, IEEE, 2020, pp. 1-6


Logic Fault Diagnosis of Hidden Delay Defects

S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC'20), November 2020, 2020


2019

A Hybrid Space Compactor for Varying X-Rates

M.U. Maaz, A. Sprenger, S. Hellebrand, 31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'19), 2019


Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test

A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers (2019), 28(1), pp. 1-23

DOI


A Hybrid Space Compactor for Adaptive X-Handling

M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1-8

The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors.


Built-in Test for Hidden Delay Faults

M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2019), 38(10), pp. 1956 - 1968

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.


2018

Stochastische Kompaktierung für den Hochgeschwindigkeitstest

A. Sprenger, S. Hellebrand, 30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'18), 2018


Design For Small Delay Test - A Simulation Study

M. Kampmann, S. Hellebrand, Microelectronics Reliability (2018), 80, pp. 124-133


Guest Editors' Introduction - Special Issue on Approximate Computing

S. Hellebrand, J. Henkel, A. Raghunathan, H. Wunderlich, IEEE Embedded Systems Letters (2018), 10(1), pp. 1-1

DOI


Extending Aging Monitors for Early Life and Wear-Out Failure Prevention

C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H. Wunderlich, in: 2018 IEEE 27th Asian Test Symposium (ATS), 2018

DOI


Tuning Stochastic Space Compaction to Faster-than-at-Speed Test

A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018

DOI


2017

Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test

M. Kampmann, S. Hellebrand, in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2017

DOI


Special Session on Early Life Failures

J. Deshmukh, W. Kunz, H. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS'17), IEEE, 2017

DOI



2016

X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test

M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS'16), IEEE, 2016, pp. 1-6

DOI


2015

Optimized Selection of Frequencies for Faster-Than-at-Speed Test

M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS'15), IEEE, 2015, pp. 109-114

DOI


A High Performance SEU Tolerant Latch

Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) (2015), 31(4), pp. 349-359


Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler

S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H. Wunderlich, 2015


2014

FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects

S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H. Wunderlich, in: IEEE International Test Conference (ITC'14), IEEE, 2014

DOI


SAT-Based ATPG beyond Stuck-at Fault Testing

S. Hellebrand, H. Wunderlich, DeGruyter Journal on Information Technology (it) (2014), 56(4), pp. 165-172


Adaptive Bayesian Diagnosis of Intermittent Faults

L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) (2014), 30(5), pp. 527-540


2013

Adaptive Test and Diagnosis of Intermittent Faults

A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H. Wunderlich, 2013


Analyzing and Quantifying Fault Tolerance Properties

S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW'13), IEEE, 2013

DOI


2012

Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test

A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW'12), IEEE, 2012, pp. 1-4

DOI


Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test

A. Cook, S. Hellebrand, H. Wunderlich, in: 17th IEEE European Test Symposium (ETS'12), IEEE, 2012, pp. 1-6

DOI



2011

Towards Variation-Aware Test Methods

I. Polian, B. Becker, S. Hellebrand, H. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS'11), IEEE, 2011

DOI


Variation-Aware Fault Modeling

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, {SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer} (2011), 54(4), pp. 1813-1826


Robuster Selbsttest mit Diagnose

A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich, in: 5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf", 2011, pp. 48-53


Diagnostic Test of Robust Circuits

A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS'11), IEEE, 2011, pp. 285-290

DOI


2010

Variation-Aware Fault Modeling

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, in: {19th IEEE Asian Test Symposium (ATS'10)}, {IEEE}, 2010, pp. 87-93

DOI


Reusing NoC-Infrastructure for Test Data Compression

V. Froese, R. Ibers, S. Hellebrand, in: {28th IEEE VLSI Test Symposium (VTS'10)}, {IEEE}, 2010, pp. 227-231

DOI


Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, in: {4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper)}, 2010


Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz

M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2010, pp. 81-88


Efficient Test Response Compaction for Robust BIST Using Parity Sequences

T. Indlekofer, M. Schnittger, S. Hellebrand, in: {28th IEEE International Conference on Computer Design (ICCD'10)}, {IEEE}, 2010, pp. 480-485

DOI


Testdatenkompression mit Hilfe der Netzwerkinfrastruktur

V. Fröse, R. Ibers, S. Hellebrand, 2010


The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems

M. Hunger, S. Hellebrand, in: {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10)}, {IEEE}, 2010, pp. 101-108

DOI


Nano-Electronic Systems

S. Hellebrand, 2010


Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W'10), IEEE, 2010

DOI


Robuster Selbsttest mit extremer Kompaktierung

T. Indlekofer, M. Schnittger, S. Hellebrand, in: {4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}, 2010, pp. 17-24


2009

Are Robust Circuits Really Robust?

S. Hellebrand, M. Hunger, in: {24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk)}, {IEEE}, 2009, pp. 77

DOI


ATPG-Based Grading of Strong Fault-Secureness

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {15th IEEE International On-Line Testing Symposium (IOLTS'09)}, {IEEE}, 2009

DOI


Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}, 2009


2008

Modularer Selbsttest und optimierte Reparaturanalyse

P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}, 2008



A Modular Memory BIST for Optimized Memory Repair

P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster)}, {IEEE}, 2008

DOI


Verification and Analysis of Self-Checking Properties through ATPG

M. Hunger, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS'08)}, {IEEE}, 2008

DOI



Signature Rollback - A Technique for Testing Robust Circuits

U. Amgalan, C. Hachmann, S. Hellebrand, H. Wunderlich, in: {26th IEEE VLSI Test Symposium (VTS'08)}, {IEEE}, 2008, pp. 125-130

DOI


Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG

M. Hunger, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}, 2008


2007

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07)}, {IEEE}, 2007, pp. 50-58

DOI


Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), (Invited Paper)}, 2007


An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip

M. Ali, S. Hessler, M. Welzl, S. Hellebrand, {International Journal on High Performance Systems Architecture} (2007), 1(2), pp. 113-123


Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair

P. Oehler, S. Hellebrand, H. Wunderlich, in: {10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07)}, {IEEE}, 2007, pp. 185-190

DOI



A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip

M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: {4th International Conference on Information Technology: New Generations (ITNG'07)}, 2007, pp. 1027-1032



Test und Zuverlässigkeit nanoelektronischer Systeme

B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich, in: {1. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}, 2007


An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy

P. Oehler, S. Hellebrand, H. Wunderlich, in: {12th IEEE European Test Symposium (ETS'07)}, {IEEE}, 2007, pp. 91-96

DOI



Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, {Informacije MIDEM, Ljubljana (Invited Paper)} (2007), 37(4 (124)), pp. 212-219



2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme

B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich, {it -Information Technology} (2006), 48(5), pp. 305-311


2005


A Dynamic Routing Mechanism for Network on Chip

M. Ali, M. Welzl, S. Hellebrand, in: {23rd IEEE NORCHIP Conference}, {IEEE}, 2005, pp. 70-73

DOI


Considerations for Fault-Tolerant Networks on Chips

M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: {IEEE International Conference on Microelectronics (ICM'05)}, {IEEE}, 2005

DOI


Low Power Embedded DRAMs with High Quality Error Correcting Capabilities

P. Oehler, S. Hellebrand, in: {10th IEEE European Test Symposium (ETS'05)}, {IEEE}, 2005, pp. 148-153

DOI


Dynamic Routing: A Prerequisite for Reliable NoCs

M. Ali, M. Welzl, S. Hellebrand, 2005


2004

Data Compression for Multiple Scan Chains Using Dictionaries with Corrections

A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC'04)}, {IEEE}, 2004, pp. 926-935

DOI


Im Westen viel Neues - Informatik an der Universität Innsbruck

R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, 2004


Data Compression for Multiple Scan Chains Using Dictionaries with Corrections

S. Hellebrand, A. Wuertenberger, C. S. Tautermann, 2004


2003

A Hybrid Coding Strategy for Optimized Test Data Compression

A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC'03)}, {IEEE}, 2003, pp. 451-459

DOI



2002

A Mixed-Mode BIST Scheme Based on Folding Compression

H. Liang, S. Hellebrand, H. Wunderlich, {Journal on Computer Science and Technology} (2002), 17(2), pp. 203-212


Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

S. Hellebrand, H. Liang, H. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} (2002), 18(2), pp. 157-168


Efficient Online and Offline Testing of Embedded DRAMs

S. Hellebrand, H. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, {IEEE Transactions on Computers} (2002), 51(7), pp. 801-809

DOI



2001

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H. Liang, H. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} (2001), 17(3/4), pp. 341-349



Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

H. Liang, S. Hellebrand, H. Wunderlich, in: {IEEE International Test Conference (ITC'01)}, {IEEE}, 2001, pp. 894-902

DOI


Deterministic BIST Scheme Based on Reseeding of Folding Counters

H. Liang, S. Hellebrand, H. Wunderlich, {Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan)} (2001), 38(8), pp. 931


2000

Hardwarepraktikum im Diplomstudiengang Informatik

S. Hellebrand, H. Wunderlich, 2000


A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H. Liang, H. Wunderlich, 2000


A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H. Liang, H. Wunderlich, in: {IEEE International Test Conference (ITC'00)}, {IEEE}, 2000, pp. 778-784

DOI


1999

Error Detecting Refreshment for Embedded DRAMs

S. Hellebrand, H. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: {17th IEEE VLSI Test Symposium (VTS'99)}, {IEEE (Comput. Soc.)}, 1999, pp. 384-390

DOI


Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren

S. Hellebrand, Verlag Dr. Kovac, Hamburg, 1999


Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms

V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H. Wunderlich, in: {Third European Dependable Computing Conference (EDCC-3)}, 1999


Symmetric Transparent BIST for RAMs

S. Hellebrand, H. Wunderlich, V. N. Yarmolik, in: {Design, Automation and Test in Europe (DATE'99)}, 1999, pp. 702-707


Exploiting Symmetries to Speed Up Transparent BIST

S. Hellebrand, H. Wunderlich, V. N. Yarmolik, 1999


1998

New Transparent RAM BIST Based on Self-Adjusting Output Data Compression

V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H. Wunderlich, in: {Design \& Diagnostics of Electronic Circuits \& Systems}, 1998, pp. 27-33


Fast Self-Recovering Controllers

A. Hertwig, S. Hellebrand, H. Wunderlich, in: {16th IEEE VLSI Test Symposium (VTS'98)}, {IEEE (Comput. Soc.)}, 1998, pp. 296-302

DOI


Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications

S. Hellebrand, A. Hertwig, H. Wunderlich, {IEEE Design and Test} (1998), 15(4), pp. 36-41


Mixed-Mode BIST Using Embedded Processors

S. Hellebrand, H. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, {Kluwer Academic Publishers}, 1998


Efficient Consistency Checking for Embedded Memories

V. N. Yarmolik, S. Hellebrand, H. Wunderlich, 1998


Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs

S. Hellebrand, H. Wunderlich, V. N. Yarmolik, in: {IEEE Design, Automation and Test in Europe (DATE'98)}, {IEEE (Comput.Soc)}, 1998, pp. 173-179

DOI


Mixed-Mode BIST Using Embedded Processors

S. Hellebrand, H. Wunderlich, A. Hertwig, {Journal of Electronic Testing Theory and Applications - JETTA} (1998), 12(1/2), pp. 127-138


Efficient Consistency Checking for Embedded Memories

V. N. Yarmolik, S. Hellebrand, H. Wunderlich, 1998


Test und Synthese schneller eingebetteter Systeme

S. Hellebrand, H. Wunderlich, 1998


1997


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