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Foto: Universität Paderborn

Prof. Dr.-Ing. J. Christoph Scheytt

Prof. Dr.-Ing. J. Christoph Scheytt

Schaltungstechnik (SCT) / Heinz Nixdorf Institut

Fachgruppeninhaber - Professor

+49 5251 60-6350
+49 5251 60-6351
Fürstenallee 11
33102 Paderborn

Liste im Research Information System öffnen


Register and Instruction Coverage Analysis for Different RISC-V ISA Modules

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021), 2021

A 2-20-GHz Ultralow Phase Noise Signal Source Using a Microwave Oscillator Locked to a Mode-Locked Laser

M. Bahmanian, C. Scheytt, IEEE Transactions on Microwave Theory and Techniques (2021), 69(3), pp. 1635-1645

Phase Noise Investigation for a Radar System with Optical Clock Distribution

S. Kruse, M. Bahmanian, P. Kneuper, C. Kress, H.G. Kurz, T. Schneider, C. Scheytt, in: The 17th European Radar Conference, 2021

Sensory Substitution Device for the Visually Impaired Using 122 GHz Radar and Tactile Feedback

P. Kneuper, S. Kruse, B. Luchterhandt, J. Tünnermann, I. Scharlau, C. Scheytt, in: The 17th European Radar Conference, 2021

Silicon Photonic Radar Transmitter IC for mm-Wave Large Aperture MIMO Radar Using Optical Clock Distribution

S. Kruse, S. Gudyriev, P. Kneuper, T. Schwabe, H.G. Kurz, C. Scheytt, IEEE Microwave and Wireless Components Letters (2021), 31(6), pp. 783-786


Sensitivity Analysis of a Low-Power Wake-Up Receiver Using an RF Barker Code SAW Correlator and a Baseband Narrowband Correlator

S. Abughannam, C. Scheytt, in: IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2020) , IEEE, 2020

In this paper we propose a novel low-power receiver architecture which uses a direct-detection receiver in combination with a 2.44 GHz 13 bit Barker Code SAW correlator for improvement of co-channel interference. Furthermore, to improve receiver sensitivity, a narrowband baseband correlator which uses pulse position modulation (PPM) is proposed. The receiver can be used as a Wake-up Receiver (WuRx) in Wireless Sensor Networks (WSN) to minimize the power dissipation and provide asynchronous and on-demand data communication. We present a rigorous analysis of the receiver. It shows that the RF front-end (SAW correlator and envelope detector) alone suffers from poor sensitivity due to the high baseband bandwidth and the absence of an RF low noise amplifier. However, by adding the narrowband correlator with an innovative Pulse Position Modulation (PPM) scheme, the overall sensitivity of the receiver reaches -63.1 dB with an improvement of 17.7 dB due to the use of the narrowband correlator that reduces the baseband bandwidth from 50 to 0.84 MHz. By scaling the narrowband correlator bandwidth further down, the receiver sensitivity can be further improved.

A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020

Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.

28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology

M. Iftekhar, S. Gudyriev, C. Scheytt, in: 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), IEEE, 2020

A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a 0.25 μm monolithic photonic BiCMOS technology. The core chip area is 0.51 mm 2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies.

Design and Fabrication of Barker Coded Surface Acoustic Wave (SAW) Correlator at 2.45 GHz for Low-Power Wake-up Receivers

S. Ballandras, S. Abughannam, E. Courjon, C. Scheytt, in: GeMiC 2020 - German Microwave Conference, 2020

Low-power receivers use direct-detection receiver architecture for its design simplicity and its low power dissipation. However, the direct-detection based receivers suffer from co-channel interference which significantly degrades the communication reliability. Co-channel interference robustness can be improved by using a BPSK Barker code modulated Surface Acoustic Wave (SAW) correlator as a prior stage to the RF direct detection circuit. This paper reports in details the design, fabrication and measurements of a 2.45 GHz SAW correlator with 13 bits length Barker code. The device is fabricated on Lithium Niobate LiNbO3 substrate and it is composed of an input non-coded Inter Digital Transducers (IDT), a Piezoelectric substrate and an output coded IDT. The device wavelength λ is set to 1.6 μm, considering a phase velocity of the wave equal to 3970 m.s-1. Several configurations of the device were designed and fabricated, particularly varying the aperture and the non-coded IDT length to find out the optimal device configuration. All devices were found to operate with Insertion Loss (IL) ranging from 12 to 15 dB at 2.45 GHz with a tip probing measurement setup, while a packaged sample has an IL of 12.45 dB at 2.44 GHz mounted on a PCB with external 50 Ω LC matching network. Additionally, time-domain measurement for the packaged device shows that the output has a correlation peak with a peak-to-side-lobe (PSL) ratio of 4:1 for a -0.5 dBm input BPSK Barker code signal.

Wide-Band Frequency Synthesizer with Ultra-Low Phase Noise Using an Optical Clock Source

M. Bahmanian, S. Farkhondehkhouy Fard, B. Koppelmann, C. Scheytt, in: 2020 IEEE/MTT-S International Microwave Symposium (IMS), IEEE, 2020

This paper presents an ultra-wideband and ultra-low noise frequency synthesizer using a mode-locked laser as its reference. The frequency synthesizer can lock in the frequency range from 2 GHz to 20 GHz on any harmonic of a mode-locked laser optical pulse train. The integrated rms-jitter (1 kHz-100 MHz) of the synthesizer is less than 5 fs in the frequency range from 4 GHz to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband phase locked loop achieving sub-10 fs rms-jitter for offset frequencies larger than 1 kHz.

Analysis, Design and Implementation of a Fully Integrated Analog Front-End for Microwave RFIDs at 5.8 GHz to be Used with Compact MIMO Readers

S. Haddadian, C. Scheytt, IEEE Journal of Radio Frequency Identification (2020), pp. 1-1

In this paper we present the system and circuit level analysis and feasibility study of applying microwave Radio Frequency Identification (RFID) systems with multipleinput multiple-output (MIMO) reader technology for tracking machining tools in multipath fading conditions of production environments. In the proposed system the MIMO reader interrogates single-antenna tags, and a high RFID frequency of 5.8 GHz is chosen to reduce the size of the reader's antenna array. According to the requirements dictated by the performed system analysis at 5.8 GHz, a low power fully integrated analog frontend (AFE) is designed and fabricated in a standard 65-nm CMOS technology for low power passive transponders. Performance of the Differential Drive Rectifier (DDR) topology as the core of the energy harvesting unit is investigated in detail. A multi-stage DDR power scavenging unit is dimensioned to provide a 1.2 V rectified voltage for 20-30 kQ load range, with a high power conversion efficiency (PCE) for high frequency and low input power level signals. The rectified voltage is then converted to a 1 V regulated voltage for the AFE and the baseband processor with 30 to 50 μW of estimated power consumption. Transistors with standard threshold voltage (VT) have been used for implementation. Measurements of the fabricated multi-stage configuration of the circuit show a maximum PCE of 68.8% at -12.46 dBm, and an input quality factor (Q-factor) of approximately 10. Amplitude-shift keying (ASK) demodulator and backscattering modulator with 80% modulation index, operating according to EPC-C1G2 protocol are applied for data transfer. The AFE consumes less than 1 μW in the reading mode. The AFE tag chip is 0.55 × 0.58 mm 2 .

Ultra-Low Phase Noise Frequency Synthesis for THz Communications Using Optoelectronic PLLs

C. Scheytt, D. Wrana, M. Bahmanian, I. Kallfass, in: 2020 Third International Workshop on Mobile Terahertz Systems (IWMTS), 2020

Recently it has been demonstrated that an optoelectronic phase-locked loop (OEPLL) using a mode-locked laser as a reference oscillator achieves significantly lower phase noise than conventional electronic frequency synthesizers. In this paper a concept for an OEPLL-based frequency synthesizer is presented and it is investigated how it can be used as a local oscillator (LO) for THz transceivers in order to improve the signal quality in THz wireless communications. The concept of the OEPLL is presented and it's measured phase noise is compared to the phase noise of a laboratory-grade electronic frequency synthesizer. The measured phase noise spectra of both synthesizers at 10 GHz are then used to model LO phase noise at 320 GHz. Based on models of generic zero-IF transmit and receive frontends, THz signals with different modulation formats and Baud rates are simulated at system level using the modeled LO phase noise for the two LO approaches. Finally, the results are compared.

Mode-locked laser timing jitter limitation in optically enabled frequency-sliced ADCs

A. Zazzi, J. Müller, S. Gudyriev, P. Marin-Palomo, D. Fang, C. Scheytt, C. Koos, J. Witzens, in: 21. ITG-Fachtagung Photonische Netze, VDE-Verlag, 2020

Novel analog-to-digital converter (ADC) architectures are motivated by the demand for rising sampling rates and effective number of bits (ENOB). The main limitation on ENOB in purely electrical ADCs lies in the relatively high jitter of oscillators, in the order of a few tens of fs for state-of-the-art components. When compared to the extremely low jitter obtained with best-in-class Ti:sapphire mode-locked lasers (MLL), in the attosecond range, it is apparent that a mixed electrical-optical architecture could significantly improve the converters' ENOB. We model and analyze the ENOB limitations arising from optical sources in optically enabled, spectrally sliced ADCs, after discussing the system architecture and implementation details. The phase noise of the optical carrier, serving for electro-optic signal transduction, is shown not to propagate to the reconstructed digitized signal and therefore not to represent a fundamental limit. The optical phase noise of the MLL used to generate reference tones for individual slices also does not fundamentally impact the converted signal, so long as it remains correlated among all the comb lines. On the other hand, the timing jitter of the MLL, as also reflected in its RF linewidth, is fundamentally limiting the ADC performance, since it is directly mapped as jitter to the converted signal. The hybrid nature of a photonically enabled, spectrally sliced ADC implies the utilization of a number of reduced bandwidth electrical ADCs to convert parallel slices, resulting in the propagation of jitter from the electrical oscillator supplying their clock. Due to the reduced sampling rate of the electrical ADCs, as compared to the overall system, the overall noise performance of the presented architecture is substantially improved with respect to a fully electrical ADC.

Fundamental limitations of spectrally-sliced optically enabled data converters arising from MLL timing jitter

A. Zazzi, J. Müller, S. Gudyriev, P. Marin-Palomo, D. Fang, C. Scheytt, C. Koos, J. Witzens, Opt. Express (2020), 28

The effect of phase noise introduced by optical sources in spectrally-sliced optically enabled DACs and ADCs is modeled and analyzed in detail. In both data converter architectures, a mode-locked laser is assumed to provide an optical comb whose lines are used to either synthesize or analyze individual spectral slices. While the optical phase noise of the central MLL line as well as of other optical carriers used in the analyzed system architectures have a minor impact on the system performance, the RF phase noise of the MLL fundamentally limits it. In particular, the corresponding jitter of the MLL pulse train is transferred almost one-to-one to the system-level timing jitter of the data converters. While MLL phase noise can in principle be tracked and removed by electronic signal processing, this results in electric oscillator phase noise replacing the MLL jitter and is not conducive in systems leveraging the ultra-low jitter of low-noise mode-locked lasers. Precise analytical models are derived and validated by detailed numerical simulations.

Analysis and Simulation of a Wireless Phased Array System with Optical Carrier Distribution and an Optical IQ Return Path

S. Kruse, C. Kress, C. Scheytt, H.G. Kurz, T. Schneider, in: GeMiC 2020 - German Microwave Conference, 2020

In this paper we present a new system concept for an optoelectronic wireless phased array system. Like in a conventional phased array system with optical carrier distribution, optical fibers are used to distribute the carrier from the basestation to the wireless frontends. However in contrast to prior concepts, we propose to use an optical IQ return path from the wireless frontends back to the basestation. Furthermore, we reuse the optical carrier signal for the IQ return path which allows to avoid local oscillator lasers in the wireless frontends and reduces the hardware effort significantly. The system concept allows to integrate all components of an optoelectronic wireless frontend in a single chip using silicon photonics technology.

Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology

L. Wu, M. Weizel, C. Scheytt, in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2020

This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding 60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375 mW.


RISC-V Extensions for Bit Manipulation Instructions

B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019

Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.

Analyse sicherheitskritischer Software für RISC-V Prozessoren

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019), 2019

In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann.

An overview of the Meteracom Project

D. Humphreys, M. Berekovic, I. Kallfass, C. Scheytt, T. Kuerner, A. Jukan, T. Schneider, T. Kleine-Ostmann, M. Koch, R. Thomae, in: Proc. 43-nd Meeting of the Wireless World Research Forum (WWRF)",, 2019

We overview the 3-year Meteracom project which will provide traceability to the SI for THz communication measurement parameters. The key objectives are to develop new metrological methods to characterize the measurement systems, system components and propagation channels. The final objective is to develop metrology for functionality and signal integrity of THz communication systems; particularly device discovery and beam tracking, determination of physical layer parameters for digital transmission and real-time performance evaluation.

An IEEE 802.11 Compliant SDR-Based System for Vehicular Visible Light Communications

M.S. Amjad, C. Tebruegge, A. Memedi, S. Kruse, C. Kress, C. Scheytt, F. Dressler, in: IEEE International Conference on Communications (ICC), ICC 2019 - 2019 IEEE International Conference on Communications (ICC), 2019, pp. 1-6

We present a complete Visible Light Communication (VLC) system for experimental Vehicular VLC (V-VLC) research activities. Visible light is becoming an important technology complementing existing Radio Frequency (RF) technologies such as Cellular V2X (C-V2X) and Dedicated Short Range Communication (DSRC). In this scope, first works helped introducing new simulation models to explore V-VLC capabilities, technologies, and algorithms. Yet, experimental prototypes are still in an early phase. We aim bridging this gap with our system, which integrates a custom-made driver hardware, commercial vehicle light modules, and an Open Source signal processing implementation in GNU Radio, which explicitly offers rapid prototyping. Our system supports OFDM with a variety of Modulation and Coding Schemes (MCS) and is compliant to IEEE 802.11; this is in line with the upcoming IEEE 802.11 LC standard as well. In an extensive series of experiments, we assessed the communication performance by looking at realistic inter vehicle distances. Our results clearly show that our system supports even higher order MCS with very low error rates over long distances.

Integrated All Optical Sampling of Microwave Signals in Silicon Photonics

A. Misra, C. Kress, K. Singh, S. Preussler, C. Scheytt, T. Schneider, in: 2019 International Topical Meeting on Microwave Photonics (MWP), 2019, pp. 1-4

Optical sampling of pseudo random microwave signals with sinc-shaped Nyquist pulse sequences has been demonstrated in an integrated silicon photonics platform. An electronic-photonic, co-integrated depletion type silicon intensity modulator with high extinction ratio has been used to sample the microwave signal with a sampling rate, which corresponds to three times its RF bandwidth. Thus, a sampling rate of 21 GSa/s is achieved with a 7 GHz modulator, with 3 dBm of differential input power.

QEMU for Dynamic Memory Analysis of Security Sensitive Software

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32-34

Octave-Band Microwave Frequency Synthesizer Using Mode-Locked Laser as a Reference

M. Bahmanian, J. Tiedau, C. Silberhorn, C. Scheytt, in: 2019 International Topical Meeting on Microwave Photonics (MWP), 2019, pp. 1-4

An octave-band voltage-controlled oscillator is phase-locked on the envelope of the pulse train from a mode-locked laser. The locking scheme employs a balanced Mach-Zehnder modulator with two photodiodes as a phase detector. The phase.locked loop has a loop bandwidth of approximately 1MHz and an in-band phase noise of approximately -135dBc/Hz at all frequencies. The integrated jitter from 1kHz to 100MHz is 21fs, 18.3fs and 13.8fs at 5.016GHz, 7.6GHz and 10.032GHz carrier frequencies, respectively. To the authors' knowledge, this is the best jitter performance reported for a PLL with MZM-based phase detection and the first reported PLL of this type featuring an octave-band frequency range.

QEMU Support for RISC-V: Current State and Future Releases

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (2019), (Presentation)

It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.

Integrated source-free all optical sampling with a sampling rate of up to three times the RF bandwidth of silicon photonic MZM

A. Misra, C. Kress, K. Singh, S. Preussler, C. Scheytt, T. Schneider, Opt. Express (2019), 27(21), pp. 29972-29984

Source-free all optical sampling, based on the convolution of the signal spectrum with a frequency comb in an electronic-photonic, co-integrated silicon device will be presented for the first time, to the best of our knowledge. The method has the potential to achieve very high precision, requires only low power and can be fully tunable in the electrical domain. Sampling rates of three and four times the RF bandwidths of the photonics and electronics can be achieved. Thus, the presented method might lead to low-footprint, fully-integrated, precise, electrically tunable, photonic ADCs with very high-analog bandwidths for the digital infrastructure of tomorrow.

Improving Co-Channel Interference Robustness In Direct Detection Receivers Using A Surface Acoustic Wave (SAW) Correlator

S. Abughannam, S. Farkhondehkhouy Fard, C. Scheytt, in: Asia-Pacific Microwave Conference (APMC), 2019

Using direct-detection architecture in Radio Frequency (RF) receivers allows for ultra-low power dissipation and is often used in Wake-Up receivers. Unfortunately direct-detection receivers suffer from high sensitivity to co-channel interference which reduces the communication performance and reliability. In this paper, it is shown that co-channel interference robustness of direct-detection receivers is improved by using Binary Phase Shift Keying (BPSK) Barker code modulated Surface Acoustic Wave (SAW) correlator as a prior stage to the RF envelope detector. Replacing the band select filter with SAW correlator does not result in higher receiver hardware cost. In our receiver, the SAW correlator functions as a passive signal processor, providing gain for a BPSK Barker code modulated signal, while suppressing in-band interferers. This improves the co-channel interference robustness of the direct-detection receiver while preserving its advantage of power efficiency. The concept is verified by means of a direct-detection receiver with discrete components on an RF PCB including an SAW Barker Code correlator at a center frequency of 2.44 GHz fabricated on Lithium Niobate substrate. Measurements with WiFi signals demonstrate that the interference robustness is improved by more than 10 dB compared to a conventional direct-detection receiver.

70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology

L. Wu, M. Weizel, C. Scheytt, in: Asia-Pacific Microwave Conference (APMC), 2019

This paper presents a broadband sampler IC using a current-mode integrated-and-hold-circuit (IHC) as sampling circuit. The sampler IC exhibits 1dB large-signal bandwidth of 70 GHz and excellent signal integrity on hold-mode. With a sampling rate of 5 GS/s, it achieves effective number of bits (ENOB) of 6 bit at 9.9 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP.

A 5.8 GHz CMOS Analog Front-End Targeting RF Energy Harvesting for Microwave RFIDs with MIMO Reader

S. Haddadian, C. Scheytt, in: IEEE International Conference on RFID Technology & Application (RFID-TA) , 2019

Targeting the feasible application of microwave RFID systems with MIMO reader technology for tracking small objects in multipath fading conditions, we present a fully integrated Analog Front-End (AFE) designed and fabricated in a standard 65-nm CMOS technology for low power passive RFID tags in the 5.8 GHz ISM band. A differential drive power scavenging unit is dimensioned to provide a 1.2 V rectified voltage resulting in a 1 V regulated voltage for the AFE while supplying a 50 μW load. Transistors with standard threshold voltage (V th ) have been used for implementation. Measurements of the fabricated circuits show a maximum Power Conversion Efficiency (PCE) of 71.8% at -12.5 dBm, and an input quality factor (Q-factor) of approximately 10.

A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology

L. Wu, M. Weizel, C. Scheytt, in: 26th IEEE International Conference on Electronics Circuits and Systems (ICECS), 2019

This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits a record 3dB small-signal bandwidth of 70 GHz. With the high sampling rate of 40 GS/s, it achieves an effective number of bits (ENOB) of 7.5 bit at 1 GHz input frequency and an ENOB of >5 bit up to 15 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 110 mA from a -4 V supply voltage, dissipating 440 mW.


Analysis of PSSS modulation for optimization of DAC bit resolution for 100 Gbps systems

K. Karthik, L. Wimmer, A.R. Javed, A. Wolf, C. Scheytt, R. Kraemer, in: 15th International Symposium on Wireless Communication Systems (ISWCS) , IEEE, 2018

The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. In our system design, we require a DAC (Digital to Analog converters) running at 1.67 G symbols/sec. The optimization of the bit resolution of this DAC will considerably reduce the hardware implementation efforts. In this work, we presented the analytical model for PSSS modulation and deduced a mathematical formula to calculate the number of discrete level amplitudes along with their probability distribution appearing at the output of the PSSS modulated signal. The analytical analysis assists in predicting the number of the quantization level of the DAC needed at the PSSS transmitter. The theoretical analysis shows that there are in total 225 discrete levels at the output of the PSSS encoder which leads to an 8-bit resolution of DAC. In this paper, we analyzed the variation of BER (Bit Error Rate) to the clipping of low probability amplitude levels and found that there is an only slight increase of the BER when we clip off the low probability amplitude levels. Thus, there is a tradeoff involved in a minor growth of BER concerning the reduction of the DAC bit resolution. Finally, we can reduce the DAC bit resolution from 8 bits to 7 bits and thus simplify the hardware implementation efforts of DAC operating at 1.67 Gbps.

First Performance Insights on Our Noval OFDM-based Vehicular VLC Prototype

J. Koepe, C. Kaltschmidt, M. Illian, R. Puknat, P. Kneuper, S. Wittemeier, A. Memedi, C. Tebruegge, M.S. Amjad, S. Kruse, C. Kress, C. Scheytt, F. Dressler, in: 2018 IEEE Vehicular Networking Conference (VNC), IEEE, 2018

In this poster, we present the first experimental results of our OFDM-based Vehicular VLC (V-VLC) prototype. Our Bit Error Rate (BER) measurements show that for lower Modulation and Coding Schemes (MCS), the performance of our hardware-setup roughly behaves the same as it does in simulation for AWGN channel. However, for higher order MCS with high PAPR, the BER performance gets degraded due to non-linear behavior of LEDs, and deviates further from AWGN performance as the MCS order is increased. The obtained results suggest that unlike RF-Communications, where the focus is usually towards linearity of the amplifiers, for V-VLC, linearity within the whole system is required to achieve optimal performance.

64 GBd Monolithically Integrated Coherent QPSK Single Polarization Receiver in 0.25 µm SiGe-Photonic Technology

C. Kress, S. Gudyriev, H. Zwickel, J.N. Kemal, S. Lischke, L. Zimmermann, C. Koos, C. Scheytt, in: Optical Fiber Communication Conference 2018, San Diego, 2018

A monolithically integrated coherent receiver in silicon photonic technology is presented along with measurement results for constellation diagrams up to 64GBd and bandwidth of 34 GHz. To our knowledge this is the fastest single-chip coherent receiver.

Wireless Energy Harvesting in RFID Applications at 5.8 GHz ISM Band, a System Analysis

S. Haddadian, C. Scheytt, in: Electromagnetics Research Symposium, 2018

A complete system analysis for an integrated passive RFID transponder designed at 5.8 GHz range is presented, and a comprehensive set of design concerns for the rectifier circuit as the core of the harvesting block is also discussed. The system analysis is complemented by transistor-level design and simulation of harvesting circuits in a commercial 65 nm CMOS technology. A differential drive rectifier (DDR) has been selected as the most efficient harvesting topology for microwave frequency applications, which works at very low input power levels. The circuit was designed and simulated including chip layout parasitics and antenna matching circuitry. Considering the power budget of the tag chip, a power conversion efficiency of roughly 68.4% is achieved in simulation for an input RF power of around -11.26dBm.

245 GHz Subharmonic Receiver With Onchip Antenna for Gas Spectroscopy Application

Y. Mao, E. Shiju, K. Schmalz, C. Scheytt, in: Journal of Semiconductors, 2018

A 2nd transconductance subharmonic receiver for 245 GHz spectroscopy sensor applications has been proposed. The receiver consists of a 245 GHz on-chip folded dipole antenna, a CB (common base) LNA, a 2nd transconductance SHM (subharmonic mixer), and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in fT/fmax = 300/500 GHz SiGe:C BiCMOS technology. The receiver dissipates a low power of 288 mW. Integrated with the on-chip antenna, the receiver is measured on-chip with a conversion gain of 15 dB, a bandwidth of 15 GHz, and the chip will be utilized in PCB board design for gas spectroscopy sensor application.

Sensitive permittivity detector for dielectric samples at 120 GHz

J. Wessel, K. Schmalz, C. Scheytt, D. Kissinger, in: 2018 IEEE Radio and Wireless Symposium (RWS), IEEE, 2018

This work describes a dielectric sensing system applying a 120 GHz electrical interferometer for contactless permittivity measurements. The applied IC was fabricated in a 130 nm SiGe process featuring an ft and fmax of 240 GHz and 330 GHz. The on-chip system contains a 120 GHz VCO with a tuning range of 7 GHz featuring a divide-by-64 circuit to enable external PLL operation. An important feature of the IC is high-precision and high-resolution phase shifting based on a slow-wave transmission lines approach with digital control. This allows for direct digital readout ability. The on chip power detector provides DC output signals giving the opportunity to record transfer functions of the interferometer. It enables sample emulation capability by phase shift inducement in the measurement as well as a reference transmission line. The motherboard of the system provides PLL stabilization for frequency sweeps. The proposed approach is capable of automated dielectric monitoring by phase compensation.

Coherent ePIC Receiver for 64 GBaud QPSK in 0.25μm Photonic BiCMOS Technology

S. Gudyriev, C. Kress, H. Zwickel, J.N. Kemal, S. Lischke, L. Zimmermann, C. Koos, C. Scheytt, in: IEEE/OSA Journal of Lightwave Technology, 2018, pp. 1-1

In this paper, we present a monolithically integrated coherent receiver with on-chip grating couplers, 90° hybrid, photodiodes and transimpedance amplifiers. A transimpedance gain of 7.7 kΩ was achieved by the amplifiers. An opto-electrical 3 dB bandwidth of 34 GHz for in-phase and quadrature channel was measured. A real-time data transmission of 64 GBd-QPSK (128 Gb/s) for a single polarization was performed.

System Analysis of a Wake-Up Receiver Based on Surface Acoustic Wave Correlator

S. Abughannam, C. Scheytt, in: 2nd URSI AT-RASC, IEEE, 2018, pp. 1-4

This paper demonstrates system level analysis of an energy efficient Radio Frequency (RF) receiver. The receiver is based on a Surface Acoustic Wave (SAW) correlator which is used for highly linear demodulation and interferer suppression in conjunction with envelope detection for ultra-low power dissipation and hardware efficiency. The receiver is to be used in Wireless Sensor Networks (WSN) as a Wake-up Receiver (WuR) to reduce the network nodes power dissipation and provide asynchronous data communication. Low latency and high interference robustness makes this scheme interesting for industrial real-time applications. In this paper, the SAW correlator transfer function is derived, which functions as a Matched Filter (MF). Since the receiver uses envelope detection and based on the characteristic of the SAW, the receiver sensitivity is analyzed by means of a non-linear approach.

Design of an Automotive Visible Light Communications Link using a Off-The-Shelf LED Headlight

S. Kruse, C. Kress, A. Memedi, C. Tebruegge, M.S. Amjad, C. Scheytt, F. Dressler, in: ANALOG 2018 16. GMM/ITG-Fachtagung, IEEE, 2018

We present a transmitter circuit to drive a commercial Light Emitting Diode (LED)-based headlight for automotive Visible Light Communication (VLC). Based on the design of the presented transmitter (TX), we provide a design methodology for VLC TXs and make it available as Open Hardware. Furthermore, a complete wireless VLC link is built using the GNU Radio signal processing tool chain and demonstrated on an Universal Software Radio Peripheral (USRP). The Total Harmonic Distortion (THD) of the system is below 5% for a wide input voltage range and the 1 dB compression point (P1dB) is at 1.02V, which makes the circuit attractive for more advanced modulation formates like Orthogonal Frequency Division Multiplexing (OFDM) or Pulse-Amplitude Modulation (PAM).

Ultra‐broadband Signal Processing by means of Electronic‐Photonic Integration

C. Scheytt, in: 10th Sino-German Joint Symposium on Opto- and Microelectronic Devices and Circuits (SODC 2018), IEEE, 2018

Analog fault simulation automation at schematic level with random sampling techniques

L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, 2018

This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.

Electronic Photonic Integrated Circuits for Coherent and Non-Coherent Receivers

S. Gudyriev, C. Kress, C. Scheytt, in: 10th Sino-German Joint Symposium on Opto- and Microelectronic Devices and Circuits (SODC 2018), IEEE, 2018


ANALISA - A Tool for Static Instruction Set Analysis

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, 2017

System design of a mixed signal PSSS transdeiver using a linear ultra-broadband analog correlator for the receiver baseband designed in 130nm SiGe BiCMOS technology

A.R. Javed, C. Scheytt, K. Karthik, R. Kramer, in: IEEE EUROCON 2017-17th International Conference on Smart Technologies, 2017, pp. 228-233

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that is well suited for mixed-signal transceiver implementation for high data rate wireless communication systems. Mixed signal baseband realization allows for easier implementation of the channel equalization function and eliminates the need for high speed data converters. System design and architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area. An ultra-broadband analog correlator consisting of a four-quadrant multiplier and a fast resettable integrator using only NPN transistors was designed, fabricated, and measured. The correlator circuit is the core component of the receiver baseband. To the best knowledge of the authors, it is the fastest correlator circuit published so far.

Fully-Differential, Hybrid, Multi-channel 4x25Gbps Direct Direction Receiver in 0.25\textmum BiCMOS SiGe Technology

S. Gudyriev, C. Scheytt, C. Kress, L. Yan, M. Christian, L. Zimmermann, OSA Frontiers in Optics + Laser Science (2017)

A hybrid multi-channel receiver featuring fully-differential transimpedance input stages for 25Gbps data rate per channel is presented along with measurement results focusing on the channel-to-channel interference and sensitivity. OMA of -16dBm at a BER of 10−4 is estimated at the photodiode for all channels. Each channel dissipates 330mW of power provided from a single 3.3V supply voltage.

ANALISA - A Tool for Static Instruction Set Analysis

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: Design Automation and Testing in Europe (DATE), 2017

An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, pp. 44

Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen

P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017

Wissenschaftsforum Intelligente Technische Systeme (WInTeSys)

J. Gausemeier, E. Bodden, F. Dressler, R. Dumitrescu, F. Meyer auf der Heide, C. Scheytt, A. Trächtler, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2017

Das Wissenschaftsforum Intelligente Technische Systeme (WInTeSys) legt am 11. und 12. Mai 2017 in Paderborn den Schwerpunkt auf die Grundlagen und die Entwicklung intelligenter technischer Systeme im Kontext Industrie 4.0. Etwa 40 begutachtete hochkarätige Beiträge geben einen Überblick über Forschungsfelder, Technologien und Anwendungen. Die Veranstaltung bietet den Teilnehmerinnen und Teilnehmern eine ausgezeichnete Bühne für den Erfahrungsaustausch auf dem Weg in die Digitalisierung von Produkten und Produktionssystemen. »Das Besondere ist der Dialog von Hochschulforschung und industrieller Entwicklung, also das Aufeinandertreffen von »Science-Push« und »Application-Pull«. Die Beiträge spiegeln die hervorragende Vernetzung in der Region OWL und darüber hinaus wider«, sagt Veranstalter Prof. Jürgen Gausemeier (Heinz Nixdorf Institut, Universität Paderborn).

SHF RFID System for Automatic Process Optimization with Intelligent Tools

P. Kuhn, S. Haddadian, F. Meyer, M. Hoffmann, A. Grabmaier, C. Scheytt, T. Kaiser, in: Smart SysTech 2017; European Conference on Smart Objects, Systems and Technologies, VDE ITG, 2017

In this paper we present theoretical, simulated and measured data for a reader to tag communication RFID system at 5.8 GHz. First a theoretical link budget analysis for a reader to tag architecture is shown for a wireless industrial application at 1m distance. This includes a power budget of the passively powered transponder. The received power level of the backscattered data for the theoretical link budget is -52:5 dBm. For the first setup slot antennas are developed and measured in the anechoic chamber. The measured gain is 4.0 dB. The power of the backscatter data in setup 1 is -74:8 dBm. This corresponds to the theoretical link budget since, all losses such as cable or lower antenna gain are taken into account. Setup 2 is upgraded on the reader side with horn antennas. At 5.8 GHz, the gain reaches the value of 10.8 dB. The second setup shows improvement in the receiving backscattered power to a value of -62:4 dBm. Furthermore, as a solution to detect those transponders not presented in the main slope of the antenna, a steerable beam is introduced by means of a Rotman lens. On the topic of the passive transponder, different harvesting topologies at 5.8 GHz are investigated, and the efficiency simulation of the harvesting circuitry has been performed. The simulated efficiency of the implemented technique is 68 %.

Wissenschaftsforum Intelligente Technische Systeme (WInTeSys). , Band 369

J. Gausemeier, E. Bodden, F. Dressler, R. Dumitrescu, F. Meyer auf der Heide, C. Scheytt, A. Trächtler. Wissenschaftsforum Intelligente Technische Systeme (WInTeSys). , Band 369. 2017.

A 120-GHz Electrical Interferometer for Contactless Permittivity Measurements With Direct Digital Read-Out

J. Wessel, K. Schmalz, C. Scheytt, D. Kissinger, IEEE Microwave and Wireless Components Letters (2017), 27(2), pp. 198-200

This work describes an electrical interferometer for contactless permittivity measurements working at 120 GHz. It was fabricated in a 130 nm SiGe process featuring an ft and fmax of 240 and 330 GHz. The on-chip system contains a 120 GHz VCO with a tuning range of 7 GHz featuring a divide-by-64 circuit to enable external PLL operation. The subsequent buffer provides 7 dBm of output power at 120 GHz. Additionally, the IC contains high-precision and high-resolution phase shifters based on a slow-wave transmission line approach with digital control for direct readout ability. A 120 GHz LNA with 17 dB gain and a power detector to provide DC output signals were realized on chip. It enables sample emulation capability by phase shift inducement in the measurement as well as a reference transmission line. In terms of phase detection, the system shows a sensitivity of 907.36 MHz/°.

Energy Harvesting Analysis for Next Generation Passive RFID Tags

S. Haddadian, C. Scheytt, R. Kramer, in: ANALOG 2017; 16th ITG/GMM-Symposium, Technische Universität Berlin, 2017, pp. 18

This paper focuses on the design of a high efficiency cross-connected differential drive rectifier for next-generation passive RFID tags. To provide a realistic estimation of the transponders’power and efficiency requirements at 5.8 GHz, detailed link/power-budget analysis for various blocks of the tag chip is carried out. From link budget analysis realistic RF power levels are obtained and a rectifier with high conversion efficiency at low power levels is designed. Simulations based on a commercial 65nm CMOS technology investigate the suitability of the harvesting circuit for 5.8 GHz RFID tags.

Low-Power wake up receiver based on Surface Acoustic Wave Correlator

S. Abughannam, C. Scheytt, in: Kleinheubacher Tagung 2017, 2017, pp. 47

Wireless Sensor Networks (WSN) consist of large number of distributed sensors nodes which are able to sense, read and transmit physical measurements such as temperature, humidity and pressure over wireless communication links. WSN nodes are often powered by batteries or can use energy harvesting methods from environmental energy sources. One of the major challenges in the design of WSN nodes is the high level of power dissipation for sensing, processing and communication. Operating at low-power levels reduces maintenance effort for periodic battery replacement or can even provide unlimited operation by means of energy harvesting. Since the communication process is the most power hungry process, ultra-low-power wireless communication is an enabler for network applications such as cyber-physical systems, Internet-of-Things and Industry 4.0 etc. Our research is based on Wake-up Receivers (WuR) architectures. Each of the WSN nodes contains a WuR which is always-on, listening for a wake-up signal from other nodes or the base station, and activating the node only when a wake-up signal is detected. By this scheme the communication with the base station becomes asynchronous, real-time and on-demand. Due to the centrally-coordinated, collision-free communication such WSNs can be scaled to very large node numbers. Designing always-on WuR at ultra-low-power dissipation levels makes the WSN nodes very energy efficient because they are only activated when a wake-up-signal is received. Additionally, the WuR must be robust to noise and co-channel interference in order to operate safely in parallel to other wireless systems. We investigate a novel radio architecture for the WuR using Linear Frequency Modulation (LFM) and passive analog signal processing by means of a Surface Acoustic Wave (SAW) correlator. The base station sends the required WSN node ID using LFM signal at 2.4 GHz. The node ID is encoded as chirp up or chirp down signal with chirping bandwidth of 80MHz. On the receiver side, the SAW chirp correlator demodulates the received LFM signal while suppressing other wireless signals. In order to achieve proper demodulation and high Signal-to-Noise Ratio (SNR), the SAW correlator is designed to behave like a Matched Filter (MF) which boosts up the SNR. After that the signal is amplified/detected by baseband amplifier stage, it is compared with the unique ID of the node, and the node's Wake up signal is asserted accordingly. Since the SAW correlator operates completely passive, the WuR can be implemented in a very energy-efficient way, without the need to use power hungry device such as Low Noise Amplifiers (LNA) or down conversion Local Oscillators (LO)

SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study

L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, pp. 68

This paper presents the design flow of using sampling technique for fault injection on sche- matic level. The parameters used in the docu- ment to calculate the likelihood could be modi- fied by using more realistic data from the fab. With the help of the fault simulator, the whole design flow of the fault effect simulation can be realized automatically.

100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing

C. Scheytt, A.R. Javed, E.R. Bammidi, K. KrishneGowda, I. Kallfass, R. Kraemer, Frequenz* Journal of RF-Engineering and Telecommunications (2017), 71 (9-10), pp. 399-414

In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.

Fully-differential, DC-coupled, Self-biased, Monolithically-integrated Optical Receiver in 0.25μm Photonic BiCMOS Technology for Multi-channel Fiber Links

S. Gudyriev, C. Scheytt, L. Yan, M. Christian, L. Zimmermann, IEEE Bipolar/BiCMOS Circuits and Technology Meeting (2017)

A fully-differential receiver structure for fiber links is presented, in which the photodiode (PD) is DC-coupled to the transimpedance amplifier (TIA) and biased through the feedback resistors. The biasing voltage is defined by the internal structure of the input stage. Different options are suggested that allow to adjust PD biasing. Multiple architecture variants are proposed, that were implemented in 0.25μm SiGe BiCMOS technology. Initial measurement results are reported, proving the feasibility of the concept. A 25Gbps hybrid receiver designed to comply with a specific standard is also presented, featuring large horizontal eye opening of 800mV, OMA of -15dBm at BER of 10 -6 and power dissipation of 330mW from a single 3.3V power supply.


Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band

F. Nava, D. Genschow, C. Scheytt, in: DRONE Berlin 2016, 2016

Ultra-compact 122GHz Radar Sensor for Autonomous Aircrafts

F. Nava, C. Scheytt, T. Zwick, M. Pauli, B. Goettel, W. Winkler, in: 3rd International Conference on System-Integrated Intelligence, 2016

In this paper a prototype of an ultra-compact continuous-wave (CW) and frequency-modulated continuous-wave (FMCW) radar system using a highly-integrated radar chip and in-package antennas will be presented. An introduction will be given on the concept of antenna integration for millimeter-wave radar and the advantages of such systems. The radar then will be described in its main components, a 122 GHz Integrated Circuit including in-package antennas as well as the acquisition and processing system realized using flexible printed circuit board (FLEX PCB) technology. Furthermore initial measurements of the radar system will be presented and explained.

    Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study

    S. Abughannam, L. Wu, W. Müller, C. Scheytt, in: Analog 2016 - VDE, 2016

    The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.

      Electronic-Photonic System-On-Chip

      C. Scheytt, in: DFG Rundgespräch:"Disruptive system concepts using electronic-photonic integration, 2016

      Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology

      A.R. Javed, C. Scheytt, U. Von der Ahe, in: IEEE Bipolar/BiCMOS Circuits and Technology Meeting, IEEE, 2016

      An ultra-broadband analog correlator consisting of a four-quadrant multiplier and an ultra-fast resettable integrator using only NPN transistors was designed, fabricated, and measured. For the integrator, a cross-coupled transistor pair is used as a negative resistance generator. A novel ultra-fast reset circuit is implemented which allows to reset the integrator within very short time of 120 ps. The chip was fabricated using 130 nm SiGe BiCMOS technology with fT of 250 GHz and f max of 300 GHz. In the measurements carried out on printed circuit board, the correlator operated without noticeable performance degradation with inputs up to 33 Gbps which correspond to a bandwidth of more than 24 GHz. The correlator exhibits high linearity with output P1dB of more than 9.9 dBm (700 mV diff ) for both inputs. It dissipates 122.5 mW for the core circuit excluding the 50 Ω output driver. To the knowledge of the authors, the circuit represents the fastest analog correlator published so far. It can be used for spread spectrum communication, radar signal processing, and measurement applications.

        Fast Dynamic Fault Injection for Virtual Microcontroller Platforms

        P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), 2016

        Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.

          An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS

          Y. Mao, K. Schmalz, C. Scheytt, in: IEEE International Symposium on Radio-Frequency Integration Technology, 2016

          This paper presents a four stage all-transmission-line 220 GHz differential LNA in SiGe BiCMOS technology. Cascode topology is chosen for each stage. The amplifier takes advantage of microstrip transmission lines to realize the inductive load, Marshand balun, input, output, and inter-stage matching of the LNA. The LNA has a gain of 21 dB at 224 GHz, a 3 dB bandwidth of more than 6 GHz. It has a supply voltage of 3V and power dissipation of 234 mW. The amplifier is intended for the use in communication, security scanning, imaging and remote sensing at 220 GHz.

            Low-Power, Ultra-compact, Fully-differential 40Gbps Direct Detection Receiver in 0.25μm Photonic BiCMOS SiGe Technology

            S. Gudyriev, C. Scheytt, S. Meister, D. Knoll, S. Lischke, L. Zimmermann, in: IEEE Group IV Photonics Conference, 2016

            Recently electronic-photonic integrated circuits (EPIC) technology platforms became available [1] which allow fabrication of very compact and fast monolithic receivers. However, although the cointegration of electronics and photonics on the same chip allows for novel circuit topologies which could help to improve circuit performance quite often transmitter and receiver circuit design is using more or less conventional approaches. We propose a novel architecture that effectively utilizes the benefits of the EPIC technology such as: very short interconnects between the photodiode and the amplifier, symmetrical and compact photodiode structure with low operating voltages. Our architecture shown in Fig. 1 features fully-differential input stage, automatic biasing of the photodiode, DC coupling between diode and transimpedance amplifier (TIA) and very small footprint.


              System Design and Simulation of a PSSS Based Mixed Signal Transceiver for a 20 Gbps Bandwidth Limited Communication Link

              A.R. Javed, C. Scheytt, in: 1st URSI Atlantic Radio Science Conference (URSI AT-RASC 2015), 2015

              Parallel Sequence Spread Spectrum (PSSS) is a physical layer baseband technology wherein parallel data streams are transmitted simultaneously by spreading them using orthogonal codes. PSSS was selected for the wireless sensor network standard IEEE802.15.4-2006 to increase data rate and improve performance in fading channels for frequency bands below 1 GHz. Since then it has gained interest for both wireless and wired communication links.

                Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment

                K. KrishneGowda, T.. Messinger, A. Wolf, R. Kraemer, I. Kallfass, C. Scheytt, in: ICUWB 2015, 2015

                Terahertz frequency band of 0.06 - 10 THz is especially interesting for ultra-high-speed wireless communication to achieve data rates of 100 Gbps or higher. To accommodate this demand, advanced terahertz signal processing techniques need to be investigated. Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that seems to be suited for being used for ultra-high speed wireless communication since the receiver architecture is especially simple and can be implemented almost completely in analog hardware. In this paper, a PSSS modulated signal at a chip rate of 20 Gcps with a spectral efficiency of (only) 1 bit/s/Hz is transmitted using a linearity limited 240 GHz wireless frontend. PSSS transceiver models are realized offline in MATLAB/Simulink. The PSSS transmitter generates the PSSS modulated symbols that are loaded onto an Arbitrary Waveform generator (AWG) and then transmitted using the available 240 GHz wireless frontend. A Digital Storage Oscilloscope (DSO) samples and stores the received signal. The PSSS receiver performs synchronization, channel estimation and demodulation. For a coded data rate of 20 Gbps, an eye opening of 40% and a BER of 5.4·10 -5 has been measured. These results are highly promising to achieve data rates of up to 100 Gbps with PSSS modulation using a RF-frontend having higher linear operating range and thus allowing increasing the bandwidth efficiency to 4 b/s/Hz.

                  System Design Considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed Signal implementation

                  A.R. Javed, C. Scheytt, K. KrishneGowda, R. Kraemer, in: Wireless and Microwave Technology Conference (WAMICON), IEEE, 2015, pp. 1-4

                  Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology which is gaining interest for both wireless and wired multi-gigabit communication systems. PSSS is well suited for mixed signal transceiver implementation including channel equalization and allows for a reduction in power dissipation by avoiding high speed data converters. The architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area.

                    Silicon photonics 90° optical hybrid design for coherent receivers

                    S. Gudyriev, C. Scheytt, in: Kleinheubacher Tagung 2015, 2015, pp. 18

                    The recent rapid development of silicon photonics technology has spurred the process of on-chip integration of all kinds of opto-electronic components. One of the most common components of such type is the opto-electrical receiver. The monolithic implementation of the receiver could potentially have lower power consumption, higher sensitivity and bandwidth due to very short diode to amplifier connection length, which has very low parasitic capacitance and series resistance. The SiGe photodiode itself is also very compact, thus lowering the junction capacitance and improving its bandwidth. Among the different optical communication systems, coherent transmission lately received a lot of attention due to the rising requirements of the optical link capacity, and it was shown that this particular approach could benefit greatly from the monolithic integration, since the major component required for the demodulation on the receiver side – 90° optical hybrid – could be implemented fully passive and directly on the same chip as the receiver itself, together with digital post-processing circuitry. Despite the initial complexity of the modulation scheme, advanced silicon photonics components like this optical hybrid could make coherent transmission attractive even for short-range optical links. I would like to present the actual designs, implementation and measurement results of 90° fully passive optical hybrids, implemented in the IHP SG25PIC (passive photonics IC) technology. One of the designs is based on 4x4 multimode interferometer (MMI). The other one is based on two separate 2x2 MMIs with additional delay element. The final designs didn’t require any additional tuning after fabrication and have shown sufficient precision and performance for a coherent system design. The results of this work were later used for the design of monolithic coherent receiver.

                      100 Gigabit pro Sekunde und mehr für das drahtlose Hochgeschwindigkeits-Internet

                      C. Scheytt, A.R. Javed. 100 Gigabit pro Sekunde und mehr für das drahtlose Hochgeschwindigkeits-Internet. 2015.

                      Miniaturized 122 GHz ISM Band FMCW Radar with Micrometer Accuracy

                      S. Scherr, B. Göttel, S. Ayhan, A. Bhutani, M. Pauli, W. Winkler, C. Scheytt, T. Zwick, in: European Microwave Week 2015, 2015

                      In this paper, a miniaturized 122 GHz ISM band FMCW radar is used to achieve micrometer accuracy. The radar consists of a SiGe single chip radar sensor and LCP off-chip antennas. The antennas are integrated in a QFN package. To increase the gain of the radar, an additional lens is used. A combined frequency and phase evaluation algorithm provides micrometer accuracy. The influence of the lens phase center on the beat frequency phase and hence, the overall accuracy is shown. Furthermore, accuracy limitations of the radar system over larger measurement distances are investigated. Accuracies of 200 μm and 2 μm are achieved over a distance of 1.9 m and 5 mm, respectively.

                        On the Correlation of HW Faults and SW Errors

                        W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015

                        Mixed-Signal Baseband Processing for 100 Gbit/s Communications

                        C. Scheytt, A.R. Javed, in: European Microwave Week 2015, 2015

                        Mixed-mode Baseband for 100 Gbit/s Wireless Communications

                        A.R. Javed, C. Scheytt, R. Kraemer, T. Messinger, I. Kallfass, 2015


                        mm-Wellen- und Electronic-Photonic System-on-Chip Design

                        C. Scheytt, in: Fakultätskolloquium der Fakultät für Elektrotechnik und Informationstechnik, 2014

                        A -Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology

                        M. Elkhouly, Y. Mao, C. Meliani, C. Scheytt, F. Ellinger, IEEE JOURNAL OF SOLID-STATE CIRCUITS (2014), 49(9)

                        100 Gb/s: PHY layer Overview and Challenges in THz freqency band

                        R. Kraemer, A. Wolf, C. Scheytt, I. Kallfass, in: 2014 IEEE 15th Annual IEEE Wireless and Microwave Technology Conference (WAMICON), IEEE, 2014

                        There is a continuous increase of bandwidth-demanding services such as ultra HDTV, 3D TV, etc. which will require data rates up to 100-400 Gb/s for short range wireless communication. This paper introduces a novel mixed-mode design where both analog and digital domain design is considered, which helps in the reduction of power consumption. Parallel Sequence Spread Spectrum (PSSS) is used for physical layer (PHY) baseband technology, which considerably alleviates both transmitter and receiver design.

                          Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU

                          B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014)

                          Switchable slow wave transmission line in 130 nm SiGe technology at 115 GHz for phase detection based biosensors

                          J. Wessel, K. Schmalz, C. Scheytt, C. Meliani, in: Microwave Symposium (IMS), 2014 IEEE MTT-S International, IEEE, 2014, pp. 1 - 3

                          A 115 GHz slow wave transmission line intended for phase detection based integrated biosensors is presented. The structure was fabricated in a 130 nm SiGe process. It achieved the targeted overall phase shift of 1° at 115 GHz. Moreover, the phase can be adjusted by 16 switches using Heterojunction Bipolar (HBT) transistors leading to a phase resolution of 0.125°. The change in input and output matching over all configurations of the switches is not higher than 0.8 dB and the transmission S 21 varies with less than 0.7 dB. To the authors knowledge, it is the first switchable slow wave structure using microstrip transmission lines along with a bipolar switch circuitry. Moreover, the presented structure provides a very powerful solution for real-time digital read-outs in integrated biosensors, without need of additional signal processing steps.

                            A 7 GHz biosensor for permittivity change with enhanced sensitivity through phase compensation

                            J. Wessel, K. Schmalz, C. Scheytt, C. Meliani, B. Cahill, in: European Microwave Conference (EuMC), IEEE, 2014, pp. 699 - 702

                            A calibration technique as well as measurement results for a 7 GHz Biosensor are presented. It is shown that the applied sensor structure can be calibrated by adjusting the phase of a sensing element's transmission S21. This is realized by slowing down the wave traveling a microstrip line serving as a reference in the differential sensor structure. The dielectric properties along with certain physical boundaries of an obstacle covering parts of the microstrip line evoke that effect. Measurements with an ethanol serious along with simulation results showed that sensitivity can be increased substantially with this calibration technique. A change of the real part of the sample's permittivity of 48 leads to a 18 MHz frequency shift.

                              Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer

                              A. Awny, L. Möller, J. Junio, C. Scheytt, A. Thiede, IEEE JOURNAL OF SOLID-STATE CIRCUITS (2014), Vol.49(No.2), pp. 452-470

                              A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.

                                System-on-Chip Design für Funkfrequenzen oberhalb von 100 GHz-Herausforderungen und potenzielle Anwendungen

                                C. Scheytt, in: Analog 2014,14. Fachtagung der Gesellschaft für Mikroelektronik, Mikrosystemtechnik und Feinwerktechnik des VDE und VDI, 2014

                                Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU

                                B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, J.C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014)

                                Design of an Electrical Interferometer at 120 GHz for Contactless Permittivity Characterization

                                J. Wessel, K. Schmalz, B. Cahill, C. Scheytt, in: Elektrotechnisches Kolloquium, 2014


                                A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology

                                B. Laemmle, K. Schmalz, J. Borngräber, C. Scheytt, R. Weigel, A. Koelpin, D. Kissinger, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on, 2013

                                A fully integrated six-port receiver front-end at 120 GHz center frequency including a low-noise-amplifier, a passive six-port network, a VCO, and four direct converters is presented in this publication. The overall architecture of the designed six-port receiver is analyzed and fundamental theory of the receiver given. The design of the six-port building blocks is described and measurement results are presented. All circuits have been fabricated in a 0.13μm 300-GHz f T SiGe BiCMOS technology. The fully integrated receiver consumes 85.9 rnA from a 3.3-V supply and occupies an area of 1.03mm 2 . The receiver includes a VCO with a center frequency of 117.15 GHz, a tuning range of 2.7 GHz, and a phase noise of -86 dBc/Hz at 1 MHz offset. The LNA shows a gain of 12 dB, a 3-dB bandwidth of 30 GHz at a power consumption of 9.2 rnA. The six-port core has a conversion gain of 3.6 dB, a P 1dB of -12 dBm, and a power consumption of 28 rnA. The overall receiver shows a conversion gain of 2.4 dB at 120 GHz and P 1dB of -17 dBm.

                                  Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\circ Hybrid With Different Input Frequencies

                                  J. Kuo, C. Lien, Z. Tsai, K. Lin, K. Schmalz, C. Scheytt, H. Wang, Microwave Theory and Techniques, IEEE Transactions on (2013), 60(8), pp. 2473-2485

                                  In this paper, a novel 180°hybrid with different input frequencies is proposed to combine RF and local oscillator (LO) signals with different frequencies in a gate/base-pumped harmonic mixer. The detailed analysis and design procedures are presented in this paper. To further reduce the chip size, the multilayer metallization above the lossy silicon substrate is employed to implement the hybrid. A V-band down-converted 2× harmonic mixer in 90-nm CMOS process and a D-band down-converted 4× harmonic mixer in the 130-nm SiGe process are designed, fabricated, and measured to verify the concept. The 2× harmonic mixer possesses 0-dB conversion gain at 60 GHz with 0-dBm LO power with merely 2.4-mW dc power. The 4× harmonic mixer achieves 0.5-dB conversion gain at 120 GHz with 2-dBm LO power and 27.3-mW dc power. With the proposed reduced-size 180° hybrid, gate/base-pumped harmonic mixers are very attractive in transceivers demanding low LO frequency and power.

                                    Flip-Chip Package with Integrated Antenna on a Polyimide Substrate for a 122-GHz Bistatic Radar IC

                                    S. Beer, M.G. Girma, Y. Sun, W. Winkler, W. Debski, J. Paaso, G. Kunkel, C. Scheytt, J. Hasch, T. Zwick, in: 7th EUROPEAN CONFERENCE ON ANTENNAS AND PROPAGATION, 2013

                                    This paper presents the packaging technology and the integrated antenna design for a miniaturized 122-GHz radar sensor. The package layout and the assembly process are shortly explained. Measurements of the antenna including the flip chip interconnect are presented that have been achieved by replacing the IC with a dummy chip that only contains a through-line. Afterwards, radiation pattern measurements are shown that were recorded using the radar sensor as transmitter. Finally, details of the fully integrated radar sensor are given, together with results of the first Doppler measurements.

                                      80 Gb/s Decision Feedback Equalizer for Intersymbol Interference

                                      L. Möller, A. Awny, J. Junio, C. Scheytt, A. Thiede, in: Optical Fiber Communication Conference, 2013

                                      We demonstrate the first 80 Gb/s decision feedback equalizer in various electrical and optical applications. The device, designed in SiGe:C BiCMOS 0.13 μm technology, enables error-free data recovery of heavily distorted signals transmitted at a bandwidth less than 30% of their bit rate. The fastest nonlinear electrical equalizer reported yet utilizes a novel 1-tap look-ahead architecture.

                                        Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors

                                        C. Scheytt, Y. Sun, K. Schmalz, Y. Mao, R. Wang, W. Debski, W. Winkler, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on, 2013, pp. 246-248

                                        Complex integrated 122 and 245 GHz SiGe BiCMOS transceiver ICs as well as an efficient broadband on-chip antenna are presented. The ICs target radar and sensing applications for the ISM bands at 122 and 245 GHz. Due to high level of integration and basic mm-wave self-testing production as well as test cost are dramatically reduced. Furthermore a compact and efficient on-chip antenna allows for chip-on-board mounting without RF interfaces.

                                          Analysis and minimization of substrate spurs in fractional-N frequency synthesizers

                                          S.A. Osmany, F. Herzel, C. Scheytt, Analog Integrated Circuits and Signal Processing (2013), 74(3), pp. 545-556

                                          This paper analyses substrate-related spurious tones in fractional-N phase- locked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these spurs is minimized by layout techniques shielding the reference input buffer. Spur minimization by using a variable reference frequency is experimentally demonstrated. Based on this observation, a programmable integer-N PLL for driving the fractional-N synthesizer is suggested to reduce the worst-case spur level significantly. Index Terms — Fractional-N, frequency synthesizers, fractional spurs, substrate spurs, phase-locked loops (PLLs), phase noise.

                                            Strategies for Energy-Efficient 100 Gb/s Baseband

                                            C. Scheytt, R. Kraemer, I. Kallfass, in: W 19 (EuMC \& EuMIC), 2013

                                            RF-MST Cluster Workshop on MEMSWAVE 2013

                                            C. Scheytt, in: RF-MST Cluster Workshop on MEMSWAVE 2013, 2013

                                            A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization

                                            Y. Sun, M. Marinkovic, G. Fischer, W. Winkler, W. Debski, S. Beer, T. Zwick, M.G. Girma, J. Hasch, C. Scheytt, in: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 148-149

                                            This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test (BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits and a digital interface. This chipset has been tested in a low-cost package, where the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art integration level and receiver linearity, and DC power consumption.

                                              A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology

                                              M. Elkhouly, Y. Mao, C. Meliani, F. Ellinger, C. Scheytt, in: 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,, 2013

                                              A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with f T /f max of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V.

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