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Traditionell veranstaltet das Department Chemie im Dezember die „Weihnachtsvorlesung“. Bildinformationen anzeigen
Besinnlich geht es im Audimax eher wenig zu – dafür aber umso spektakulärer. Bildinformationen anzeigen
Thema der Weihnachtsvorlesung 2018: „Nachts sind alle Katzen grau, ohne Chemie auch tagsüber – Erhellendes zu Licht und Farbe“ Bildinformationen anzeigen
Chemie gibt es nur im Hörsaal und in Laboren? Nein: Dr. Andreas Hoischen zeigt insbesondere auch chemische Prozesse aus dem Alltag. Bildinformationen anzeigen
Das Finale: keine Weihnachtsvorlesung ohne das abschließende Feuerwerk. Bildinformationen anzeigen

Zum Jahreswechsel – die Weihnachtsvorlesung der Chemie

Traditionell veranstaltet das Department Chemie im Dezember die „Weihnachtsvorlesung“.

Foto: Universität Paderborn, Adelheid Rutenburges

Zum Jahreswechsel – die Weihnachtsvorlesung der Chemie

Besinnlich geht es im Audimax eher wenig zu – dafür aber umso spektakulärer.

Foto: Universität Paderborn, Adelheid Rutenburges

Zum Jahreswechsel – die Weihnachtsvorlesung der Chemie

Thema der Weihnachtsvorlesung 2018: „Nachts sind alle Katzen grau, ohne Chemie auch tagsüber – Erhellendes zu Licht und Farbe“

Foto: Universität Paderborn, Adelheid Rutenburges

Zum Jahreswechsel – die Weihnachtsvorlesung der Chemie

Chemie gibt es nur im Hörsaal und in Laboren? Nein: Dr. Andreas Hoischen zeigt insbesondere auch chemische Prozesse aus dem Alltag.

Foto: Universität Paderborn, Adelheid Rutenburges

Zum Jahreswechsel – die Weihnachtsvorlesung der Chemie

Das Finale: keine Weihnachtsvorlesung ohne das abschließende Feuerwerk.

Foto: Universität Paderborn, Adelheid Rutenburges

Prof. Dr. Sybille Hellebrand

Kontakt
Vita
Publikationen
Prof. Dr. Sybille Hellebrand

Datentechnik (DATE)

Leiterin - Professorin

Telefon:
+49 5251 60-3002
Fax:
+49 5251 60-4227
Büro:
P1.6.08.1 (Karte)
Sprechzeiten:

nach Vereinbarung

Web:
Besucher:
Pohlweg 47-49
33098 Paderborn
Postanschrift:
Warburger Str. 100
33098 Paderborn

Geschäftsstelle

Stellvertretende Institutsleiterin - Professorin

Telefon:
+49 5251 60-3002
Fax:
+49 5251 60-4221
Büro:
P1.6.08.1 (Karte)
Web:
Besucher:
Pohlweg 47-49
33098 Paderborn
Postanschrift:
Warburger Str. 100
33098 Paderborn

07/1986 - heute

Curriculum Vitae

Sybille Hellebrand received her Diploma in Mathematics from the University of Regensburg in 1986. In the same year she joined the Institute of Computer Design and Fault Tolerance at the University of Karlsruhe, where she finished her Ph.D. in Computer Science in 1991. From 1991 to 1992 she received a post-doctoral fellowship from the French government and continued her research work at the TIM3/IMAG Laboratory in Grenoble, France. In 1992 she joined the University of Siegen as a post-doctoral research and teaching assistant. For her habilitation project she received a Lise- Meitner Fellowship from the NRW government in 1995. Before she completed her habilitation in 1997 she spent several months as a guest researcher at Mentor Graphics Corporation in Portland, OR, USA. After her stay in the USA, Sybille Hellebrand moved to the University of Stuttgart as a permanent research and teaching assistant. In 1999 she was appointed full professor in Computer Science at the University of Innsbruck, Austria.

Since December 2004 she holds the chair for Computer Engineering at the Institute of Electrical Engineering and Information Technology at the University of Paderborn. Sybille Hellebrand is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the IEEE Test Technology Technical Council (TTTC). She has served on the program committees of many international conferences, and she was the General Chair of the IEEE European Test Symposium in 2014. She is an associate editor of the Journal of Electronic Testing – Theory and Applications (JETTA). From 2002 to 2009 she was a member of the editorial board of IEEE Transactions on Computer-Aided Design of Circuits and Systems. Her main research interests are in test, diagnosis, and fault tolerance of integrated circuits and systems.

Zeitschriften und begutachtete Konferenzbände

M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich: Built-in Test for Hidden Delay Faults; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018, pp. 1-13

C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich: Extending Aging Monitors for Early Life and Wear-out Failure Prevention; accepted for Proceedings 27th IEEE Asian Test Symposium (ATS'18), Hefei, Anhui, China, 15-18 October 2018, pp. 1-6

A. Sprenger, S. Hellebrand: Tuning Stochastic Space Compaction to Faster-than-At-Speed Test; Proceedings of 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2018), Budapest, Hungary, April 2018, pp. 73-78 (Best paper award)

S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich: Guest Editors’ Introduction - Special Issue on Approximate Computing; IEEE Embedded Systems Letters, Vol. 10, No. 1, March 2018, pp. 1-1

M. Kampmann, S. Hellebrand: Design for Small Delay Test - A Simulation Study; Microelectronics Reliability 80 (2018), pp. 124-133

J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand: Special Session on Early Life Failures; Proceedings VLSI Test Symposium (VTS'17), Caesars Palace, Las Vegas, Nevada, USA, April 2017, pp. 9-12

M. Kampmann, S. Hellebrand: Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test, Proceedings 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’17), Dresden, Germany, April 2017, pp. 39–45 (Best paper award)

M. Kampmann, S. Hellebrand: X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test, Proceedings Asian Test Symposium (ATS’16), Hiroshima, Japan, Nov. 2016,
pp. 1–6.

M. Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand,
Hans-Joachim Wunderlich: Optimized Selection of Frequencies for Faster-than-at-Speed Test; Proceedings Asian Test Symposium (ATS’15), Mumbai, India, November 2015, pp. 109-114

Z. Huang, H. Liang, S. Hellebrand: A High Performance SEU Tolerant Latch; Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 31, No. 4, August 2015, pp. 349-359

L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H. Wunderlich: Adaptive Bayesian Diagnosis of Intermittent Faults; Journal of Electronic Testing - Theory and Applications (JETTA), Volume 30, Issue 5, October 2014, pp 527-540

S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich: FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects; accepted for Proc. IEEE International Test Conference, Seattle, USA, October 2014, pp. 1-8

S. Hellebrand, H.-J. Wunderlich: SAT-Based ATPG beyond Stuck-at Fault Testing; DeGruyter Journal on Information Technology (it), Vol. 56 No. 4, June 2014, pp. 165-172

A. Cook, S. Hellebrand, H.-J. Wunderlich: Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test; Proc. 17th IEEE European Test Symposium (ETS’12), Annecy, France, May 2012, pp. 1-6

A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich: Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test; Proc. Latin American Test Workshop, Quito, Ecuador, April 2012, pp. 1-4

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich: Variation-Aware Fault Modeling;

A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich: Diagnostic Test of Robust Circuits; Proc. 20th Asian Test Symposium, New Delhi, India, November, 2011, pp. 285-290

A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich: Robuster Selbsttest mit Diagnose; 5. GMM/GI/ITG Fachtagung „Zuverlässigkeit und Entwurf“, Hamburg, September 2011, pp. 48-53

Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-Aware Fault Modeling; Proceedings 19th Asian Test Symposium, Shanghai, China, December 1-4, 2010, pp. 87-93

Marc Hunger, Sybille Hellebrand: The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems; Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10), Kyoto, Japan, October 2010, pp. 101-108

Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand: Efficient Test Response Compaction for Robust BIST Using Parity Sequences; Proceedings 28th IEEE International Conference on Computer Design (ICCD'10), Amsterdam, The Netherlands, October 2010

Marc Hunger, Sybille Hellebrand: Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz; Proceedings 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Wildbad Kreuth, September 2010, pp. 81-88

Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand: Robuster Selbsttest mit extremer Kompaktierung; Proceedings 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Wildbad Kreuth, September 2010, pp. 17-24

Viktor Fröse, Rüdiger Ibers, Sybille Hellebrand: Reusing NoC-Infrastructure for Test Data Compression; Proceedings IEEE VLSI Test Symposium (VTS'10), Santa Cruz, CA, USA, April 2010, pp. 227-231

Marc Hunger, Sybille Hellebrand, Alexander Czutro, Ilia Polian, Bernd Becker: Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung; Proceedings 3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Stuttgart, September 2009, pp. 53-60

Marc Hunger, Sybille Hellebrand, Alexander Czutro, Ilia Polian, Bernd Becker: ATPG-Based Grading of Strong Fault-Secureness; IEEE International On-Line Testing Symposium 2009 (IOLTS'09), Sesimbra-Lisbon, Portugal, June 2009, pp. 269-274

M. Hunger, S. Hellebrand: Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG; GMM-Fachtagung Zuverlässigkeit und Entwurf, Ingolstadt, September 2008, pp. 67-74

P. Öhler, A. Bosio, G. Di Natale, S. Hellebrand: Modularer Selbsttest und optimierte Reparaturanalyse; GMM-Fachtagung Zuverlässigkeit und Entwurf, Ingolstadt, September 2008, pp. 49-55

M. Hunger, S. Hellebrand: Verification and Analysis of Self-Checking Properties through ATPG; IEEE International On-Line Testing Symposium 2008 (IOLTS'2008), Rhodos, Greece, July, 2008, pp. 25-30

P. Öhler, A. Bosio, G. Di Natale, S. Hellebrand: A Modular Memory BIST for Optimized Memory Repair; Proceedings IEEE International On-Line Testing Symposium 2008 (IOLTS'2008), Rhodos, Greece, July, 2008, pp. 171-172

U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich: Signature Rollback – A Technique for Testing Robust Circuits; Proceedings IEEE VLSI Test Symposium (VTS’08), San Diego, CA, USA, May, 2008, pp. 125-130

M. Ali, M. Welzl, S. Hessler, S. Hellebrand: An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip; International Journal on High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 113-123

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube: A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction; Proceedings 22nd International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, September 2007, pp. 50-58

M. Ali, M. Welzl, S. Hessler, S. Hellebrand: A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip; Proceedings 4th International Conference on Information Technology: New Generations, ITNG 2007, Las Vegas, Nevada, USA, April 2-4, 2007, pp. 1027-1032

M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand: Considerations for Fault-Tolerant Networks on Chips; Proceedings International Conference on Microelectronics, ICM’05, Islamabad, Pakistan, December 2005

M. Ali, M. Welzl, S. Hellebrand: A dynamic routing mechanism for network on chip; Proceedings 23rd IEEE NORCHIP Conference, Oulu, Finland, November 21-22, 2005, pp. 70-73

P. Öhler, S. Hellebrand: Low Power Embedded DRAMs with High Quality Error Correcting Capa­bilities; Proceedings European Test Symposium (ETS), Tallinn, Estonia, May 2005, pp. 148-153

A. Würtenberger, C. S. Tautermann, S. Hellebrand: Data Compression for Multiple Scan Chains Using Dictionaries with Corrections; Proceedings IEEE International Test Conference, Charlotte, NC, USA, 2004, pp. 926-935

A. Würtenberger, C. S. Tautermann, S. Hellebrand: A Hybrid Coding Strategy for Optimized Test Data Compression; Proceedings IEEE International Test Conference, Charlotte, NC, USA, September 30 - October 2, 2003, pp. 451-459

S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik: Efficient On- and Off-Line Testing of Embedded DRAMs; IEEE Transactions on Computers, Vol. 51, No. 7, July 2002, pp. 801-809

H.-G. Liang, S. Hellebrand, H.-J. Wunderlich: Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST; Journal of Electronic Testing Theory and Application (JETTA), Vol. 18, No. 2, April 2002, pp. 157-168

H.-G. Liang, S. Hellebrand, H.-J. Wunderlich: A mixed-mode BIST scheme based on folding compression; Journal of Computer Science and Technology, Vol. 17, No. 2, S. 203-212, 2002

H.-G. Liang, S. Hellebrand, H.-J. Wunderlich: Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST; Proceedings IEEE International Test Conference, Baltimore, MD, USA, November 2001, pp. 894-902

H.-G. Liang, S. Hellebrand, H.-J. Wunderlich: Deterministic BIST scheme based on reseeding of folding counters; Jisuanji Yanjiu yu Fazhan (Journal of Computer Research and Development), Vol. 38, No. 8, p. 931, 2001

S. Hellebrand, H.-G. Liang, H.-J. Wunderlich: A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters; Journal of Electronic Testing Theory and Applications (JETTA), Vol. 17, No. 3/4, June/August 2001, pp. 341-349

S. Hellebrand, H.-G. Liang, H.-J. Wunderlich: A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters;Proceedings IEEE International Test Conference, Atlantic City, NJ, USA, October 2000, pp. 778-784

V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich: Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms; Proceedings Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, September 15-17, 1999

S. Hellebrand, H.-J. Wunderlich, S. Ivaniuk, Y. Klimets, V. N. Yarmolik: Error Detecting Refreshment for Embedded DRAMs; Proceedings 17th IEEE VLSI Test Symposium, Dana Point, CA, USA, April 25 - April 29, 1999, pp. 384 – 390

S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik: Symmetric Transparent BIST for RAMs; Proceedings Design, Automation and Test in Europe, DATE’99, Munich, Germany, March 9-12, 1999, pp. 702 – 707

S. Hellebrand, H.-J. Wunderlich, A. Hertwig: Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications; IEEE Design & Test, Vol. 15, No. 4, October-December, 1998, pp. 36-41

V. N. Yarmolik, Y. Klimets, S. Hellebrand, H.-J. Wunderlich: New Transparent RAM BIST Based on Self-Adjusting Output Data Compression; Proceedings Design & Diagnostics of Electronic Circuits and Systems, Szczyrk, Poland, September, 1998, pp. 27-33

A. Hertwig, S. Hellebrand, H.-J. Wunderlich: Fast Self-Recovering Controllers; Proceedings 16th IEEE VLSI Test Symposium, Monterey, CA, USA, April, 1998, pp. 296-302

S. Hellebrand, H.-J. Wunderlich, A. Hertwig: Mixed-Mode BIST Using Embedded Processors; Journal of Electronic Testing Theory and Applications (JETTA), Vol. 12, Nos. 1/2, February/April 1998, pp. 127-138

V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich: Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs; Proceedings Design, Automation and Test in Europe (DATE98), Paris, France, February, 1998, pp. 173-179

K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski: STARBIST: Scan Autocorrelated Random Pattern Generation; Proceedings ACM/IEEE Design Automation Conference, Anaheim, CA, USA, June 9 - 13, 1997

S. Hellebrand, H.-J. Wunderlich, A. Hertwig: Mixed-Mode BIST Using Embedded Processors; Proceedings IEEE International Test Conference, Washington, DC, USA, October 1996, pp. 195-204

S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich: Pattern Generation for a Deterministic BIST Scheme; Proceedings IEEE/ACM International Conference on CAD-95, San Jose, CA, USA, November 1995, pp. 88-94

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois: Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers; IEEE Transactions on Computers, Vol. 44, No.2, February 1995, pp. 223-233

S. Hellebrand, H.-J. Wunderlich: An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures; Proceedings IEEE/ACM International Conference on CAD-94, San Jose, CA, USA, November 1994, pp. 110-116

S. Hellebrand, H.-J. Wunderlich: Synthese schneller selbsttestbarer Steuerwerke; Proceedings der GI/GME/ITG-Fachtagung „Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme“, Oberwiesenthal, Mai 1994 (Informatik Xpress 4, TU Chemnitz Zwickau)

S. Hellebrand, H.-J. Wunderlich: Synthesis of Self-Testable Controllers; Proceedings Proceedings European Design and Test Conference 1994, Paris, France, February 28 - March 3, 1994, pp. 580-585

S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick: An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers; Proceedings IEEE/ACM International Conference on CAD-93, Santa Clara, CA, USA, November 1993, pp. 572-577

S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois: Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers; Proceedings IEEE International Test Conference, Baltimore, MD, USA, September 1992, pp. 120-129

H.-J. Wunderlich, S. Hellebrand: The Pseudo-Exhaustive Test of Sequential Circuits; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 1, Jan. 1992, pp. 26-33

S. Hellebrand, H.-J. Wunderlich, O. F. Haberl: Generating Pseudo-Exhaustive Vectors for External Testing; Proceedings IEEE International Test Conference, Washington, DC, USA, 1990, pp. 670-679

S. Hellebrand, H.-J. Wunderlich: Tools and Devices Supporting the Pseudo-Exhaustive Test; Proceedings European Design Automation Conference, Glasgow, UK, 1990, pp. 13-17

H.-J. Wunderlich, S. Hellebrand: The Pseudo-Exhaustive Test of Sequential Circuits; Proceedings IEEE International Test Conference, Washington, DC, USA, 1989, pp. 19-27

S. Hellebrand, H.-J. Wunderlich: Automatisierung des Entwurfs vollständig testbarer Schaltungen; Proceedings der 18. Jahrestagung der Gesellschaft für Informatik II, Hamburg 1988, Informatik-Fachberichte 188, Springer Verlag, pp. 145-159

H.-J. Wunderlich, S. Hellebrand: Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits; Proceedings of the 18th International Symposium on Fault-Tolerant Computing FTCS-18, Tokyo, Japan, 1988, pp. 36-41

D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann: Integrated Tools for Automatic Design for Testability; Tool Integration and Design Environments, F. J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B. V. (North Holland), IFIP, 1988, pp. 233-258

Eingeladene Beiträge

S. Hellebrand: Analyzing and Quantifying Fault Tolerance Properties; IEEE Latin American Test Workshop, Cordoba, Argentina, April 2013

I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell: Towards Variation-Aware Test Methods; Proc. IEEE 16th European Test Symposium (ETS’11), Trondheim, Norway, May 2011, pp. 219-225

Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits; 4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), Chicago, IL, USA, June 2010

Sybille Hellebrand, Marc Hunger: Are Robust Circuits Really Robust?; Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), Chicago, IL, USA, October 2009, p. 77

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube: Testing and Monitoring Nanoscale Systems – Challenges and Strategies for Advanced Quality Assurance (Invited Paper); Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, December 2007, pp. 212-219

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube: Testing and Monitoring Nanoscale Systems – Challenges and Strategies for Advanced Quality Assurance (Invited Paper); 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, September 2007

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich: DFG Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme; it - Information Technology, Vol. 48, No. 5, 2006, pp. 304-311

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich: Test und Zuverlässigkeit nanoelektronischer Systeme; GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”, Munich, Germany, March 2007

Workshops

A. Sprenger, S. Hellebrand: Stochastische Kompaktierung für den Hochgeschwindigkeitstest; 30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'18). Freiburg, Germany, March 4-6, 2018

M. Kampmann, S. Hellebrand: ; 29. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'17). Lübeck, Germany, March 5-7, 2017

S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H. Wunderlich: ; 27. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany, March 1-3, 2015

A. Cook, L. Rodriguez-Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich: Adaptive Test of Intermittent Faults; 14th IEEE Latin American Test Workshop (LATW’13), Cordoba, Argentina, April 2013

A. Cook, S. Hellebrand, H. Wunderlich: ; 24. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'12), Cottbus, Germany, February 26-28, 2012

Viktor Fröse, Rüdiger Ibers, Sybille Hellebrand: Testdatenkompression mit Hilfe der Netzwerkinfrastruktur; 22. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10), Paderborn, Germany, February 28 – March 2, 2010

T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. Zöllin: Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit; 20. ITG/GI/GMM Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Vienna, Austria, March 2008

U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich: Testen mit Rücksetzpunkten – ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen; 20. ITG/GI/GMM Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Vienna, Austria, March 2008

M. Ali, M. Welzl, S. Hessler, S. Hellebrand: An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips; DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, April 2007

P. Öhler, S. Hellebrand, and H.-J. Wunderlich: An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy; 19. ITG/GI/GMM Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Erlangen, Germany, March 2007

P. Öhler, S. Hellebrand: A Low Power Design for Embedded DRAMs with Online Consistency Checking; Kleinheubachertagung 2005, Miltenberg, Germany, September 2005

M. Ali, M. Welzl, S. Hellebrand: Dynamic Routing: A prerequisite for reliable NoCs; 17. GI/ITG/GMM Workshop zum Thema „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Innsbruck, Austria, February/March 2005

P. Öhler, S. Hellebrand: Power Consumption versus Error Correcting Capabilities in Embedded DRAMs - A Case Study; 17. GI/ITG/GMM Workshop zum Thema „Test­methoden und Zuver­lässigkeit von Schaltungen und Systemen“, Innsbruck, Austria, February/March 2005

A. Würtenberger, C. S. Tautermann, S. Hellebrand: Data Compression for Multiple Scan Chains Using Dictionaries with Corrections; 9th IEEE European Test Symposium, Ajaccio, Corsica, France, May 22-26, 2004

S. Hellebrand, A. Würtenberger: Alternating Run-Length Coding: A Technique for Improved Test Data Compression; IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, October 2002

Hua-Guo Liang, S. Hellebrand, H.-J. Wunderlich: Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST; IEEE European Test Workshop, Stockholm, Sweden, May 2001

S. Hellebrand, Hua-Guo Liang, H.-J. Wunderlich: A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters; IEEE European Test Workshop, Cascais, Portugal, May 2000

S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik: Exploiting Symmetries to Speed Up Transparent BIST; 11. GI/ITG/GMM/IEEE Workshop zum Thema „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Potsdam, Germany, February/March 1999

V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich: Efficient Consistency Checking for Embedded Memories; 10. GI/ITG/GMM/IEEE Workshop zum Thema „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Herrenberg, Germany, March 1998

V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich: Efficient Consistency Checking for Embedded Memories; 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, March 1998

A. Hertwig, S. Hellebrand, H.-J. Wunderlich: Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications; 3rd IEEE International On-Line Testing Workshop, Crete, Greece, July 1997

K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek Sadowska: STARBIST: Scan Autocorrelated Random Pattern Generation; 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, May 1997

S. Hellebrand, H.-J. Wunderlich, A. Hertwig: Mixed-Mode BIST Using Embedded Processors; 2nd IEEE International On-Line Testing Workshop, Biarritz, France, July 1996

S. Hellebrand, H.-J. Wunderlich: Using Embedded Processors for BIST; 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, May 1996

S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich: Pattern Generation for a Deterministic BIST Scheme; 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, May 1995

S. Hellebrand, J. P. Teixeira, H.-J. Wunderlich: Synthesis for Testability – The ARCHIMEDES Approach; 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, May 1994

S. Hellebrand, H.-J. Wunderlich: Ein Verfahren zur testfreundlichen Steuerwerkssynthese; 6. ITG/GI/GME Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Vaals, NL, March 1994

S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick: Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen; 6. ITG/GI/GME Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Vaals, NL, March 1994

S. Hellebrand, H.-J. Wunderlich: Synthesis of Self-Testable Controllers; ARCHIMEDES Open Workshop on „Synthesis – Architectural Testability Support“, Montpellier, France, July 1993

S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois: Effziente Erzeugung deterministischer Muster im Selbsttest; 5. ITG/GI/GME Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“, Holzhau, Germany, March 1993

S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois: Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs; Workshop on New Directions for Testing, Montreal, Canada, May 1992

S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois: Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs; IEEE Design for Testability Workshop, Vail, CO, USA, April, 1992

S. Hellebrand, H.-J. Wunderlich, O. F. Haberl: Generating Pseudo-Exhaustive Vectors for External Testing; IEEE Design for Testability Workshop, Vail, CO, USA, April, 1990

Bücher und Buchkapitel

S. Hellebrand: Selbsttestbare Steuerwerke – Strukturen und Syntheseverfahren; Hamburg: Verlag Dr. Kovac, Hamburg, 1999

S. Hellebrand, H.-J. Wunderlich, A. Hertwig: Mixed Mode BIST Using Embedded Processors; M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers, 1998

S. Hellebrand: Vollständiger Schaltungstest; VDI Fortschritt-Berichte Reihe 10: Informatik/ Kommunikationstechnik Nr. 177, 1991

Verschiedenes

S. Hellebrand: Qualitätssicherung für Nanochips – Wie IT-Produkte zuverlässig werden; ForschungsForum Paderborn, 10. Ausgabe, 2007

R. Breu, Th. Fahringer, S. Hellebrand, D. Fensel, A. Middeldorp, and O. Scherzer: Im Westen viel Neues – Informatik an der Universität Innsbruck, OCG Journal 3/2003, pp. 30-31

Ruth Breu, Sybille Hellebrand, and Michael Welzl: Experiences from Teaching Software Development in a Java Environment; Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, July 2003, Tunis, Tunisia

S. Hellebrand, H.-J. Wunderlich: Hardwarepraktikum im Diplomstudiengang Informatik; Handbuch Lehre, Berlin: Raabe Verlag, 2000

S. Hellebrand: Deformation dicker Punkte und Netze von Quadriken; Regensburger Mathematische Schriften 9, Fakultät für Mathematik der Universität Regensburg, Regensburg, Germany, 1986

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