Scalable RISC-V Multi/Many-Core Processor Systems

The System and Circuit Technolgy Group has been involved in the design and analysis of RISC-V processors for several years. In 2017, it was the co-maintainer of the first RISC-V implementation of the QEMU CPU emulator (https://www.uni-paderborn.de/projekt/304) in cooperation with SiFive and TI. As partner of the Safe4I (https://www.uni-paderborn.de/projekt/306) and Scale4Edge (https://www.uni-paderborn.de/ project/325), RISC-V-based chips in TSMC65nm and 22FDX technology were developed for AI applications, mainly in cooperation with IHP and the University of Tübingen. In this course we also developed fast analog components with tapeouts in SG13G3 and 22FDX technology (PLL, deserializer, CDR - Clock & Data Recovery).

Since 2021, the focus of the work is on the design and analysis of highly scalable embedded RISC-V-based multi/many-core processor systems with emphasis on processor arrays with RISC-V processor cores and fault-tolerant lockstep systems.

Since 2021, the our group has been developing and analyzing scalable hardware variants of the Grid of Processing Cell (GPC) hardware architecture based on RISC-V RocketChip processor cores in cooperation with UC Irvine, USA (Prof. Dömer). While the work the group at UCI focused on functional SystemC and ISS models, our group transferred the GPC architecture to scalable NxN processor arrays based on 32-bit Rocket CPU cores with local I&D memory in FPGA implementation and chip layout. The developments were carried out using UC Berkeley's Chipyard framework with the RocketChip generator, Verilator, Firesim, and Hammer. Commercial as well as open-source EDA design tools were used. Some of the developments were on the NOCTUA2 HPC cluster in cooperation with the Paderborn Center of Parallel Computing.

Since 2025, the Circuit Technology Group has also been working with IHP to develop an open-source, scalable version of the fault-tolerant RISC-V TETRISC architecture, which allows real-time context switching between multi-core and lockstep operation. The open-source hardware is implemented as a CHISEL model based on the RocketChip SoC, which is scalable in terms of the number and configuration of processor cores and the word voter.

Publications:

ris.uni-paderborn.de/record/62108

ris.uni-paderborn.de/record/58861

ris.uni-paderborn.de/record/45778

ris.uni-paderborn.de/record/45775

Projects:

Scale4Edge www.uni-paderborn.de/projekt/325

project.edacentrum.de/scale4edge/