This paper presents a technique to extend the frequency acquisition range for bang-bang phase-detector-based clock and data recovery (CDR) circuits without an additional frequency acquisition loop or lock detection circuit. The per-manent modulation of the offset current in the CDR's integral branch enhances the acquisition range by nearly 4 times, covering the entire tuning range of the voltage controlled oscillator. The increase in power dissipation and the chip area are negligible. This technique was implemented and measured in a 28 Gbps NRZ bang-bang CDR chip to confirm the working principle. In addition to the increased acquisition range, the CDR also surpasses jitter related specifications from the OIF CEI-28G-VSR standard.

A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a 0.25 μm monolithic photonic BiCMOS technology. The core chip area is 0.51 mm 2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies.