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Digitale Infotage für Schüler*innen vom 06.-09. Februar 2023

Photo: Universität Paderborn, Adelheid Rutenburges

M.Sc. Sanaz Haddadian

M.Sc. Sanaz Haddadian

System and Circuit Technology / Heinz Nixdorf Institut

Research Associate

+49 5251 60-6355
+49 5251 60-6351
Fürstenallee 11
33102 Paderborn

Open list in Research Information System


Analysis, Design and Implementation of a Fully Integrated Analog Front-End for Microwave RFIDs at 5.8 GHz to be Used with Compact MIMO Readers

S. Haddadian, C. Scheytt, IEEE Journal of Radio Frequency Identification (2020), pp. 1-1

In this paper we present the system and circuit level analysis and feasibility study of applying microwave Radio Frequency Identification (RFID) systems with multipleinput multiple-output (MIMO) reader technology for tracking machining tools in multipath fading conditions of production environments. In the proposed system the MIMO reader interrogates single-antenna tags, and a high RFID frequency of 5.8 GHz is chosen to reduce the size of the reader's antenna array. According to the requirements dictated by the performed system analysis at 5.8 GHz, a low power fully integrated analog frontend (AFE) is designed and fabricated in a standard 65-nm CMOS technology for low power passive transponders. Performance of the Differential Drive Rectifier (DDR) topology as the core of the energy harvesting unit is investigated in detail. A multi-stage DDR power scavenging unit is dimensioned to provide a 1.2 V rectified voltage for 20-30 kQ load range, with a high power conversion efficiency (PCE) for high frequency and low input power level signals. The rectified voltage is then converted to a 1 V regulated voltage for the AFE and the baseband processor with 30 to 50 μW of estimated power consumption. Transistors with standard threshold voltage (VT) have been used for implementation. Measurements of the fabricated multi-stage configuration of the circuit show a maximum PCE of 68.8% at -12.46 dBm, and an input quality factor (Q-factor) of approximately 10. Amplitude-shift keying (ASK) demodulator and backscattering modulator with 80% modulation index, operating according to EPC-C1G2 protocol are applied for data transfer. The AFE consumes less than 1 μW in the reading mode. The AFE tag chip is 0.55 × 0.58 mm 2 .


A 5.8 GHz CMOS Analog Front-End Targeting RF Energy Harvesting for Microwave RFIDs with MIMO Reader

S. Haddadian, C. Scheytt, in: IEEE International Conference on RFID Technology & Application (RFID-TA) , 2019

Targeting the feasible application of microwave RFID systems with MIMO reader technology for tracking small objects in multipath fading conditions, we present a fully integrated Analog Front-End (AFE) designed and fabricated in a standard 65-nm CMOS technology for low power passive RFID tags in the 5.8 GHz ISM band. A differential drive power scavenging unit is dimensioned to provide a 1.2 V rectified voltage resulting in a 1 V regulated voltage for the AFE while supplying a 50 μW load. Transistors with standard threshold voltage (V th ) have been used for implementation. Measurements of the fabricated circuits show a maximum Power Conversion Efficiency (PCE) of 71.8% at -12.5 dBm, and an input quality factor (Q-factor) of approximately 10.


Wireless Energy Harvesting in RFID Applications at 5.8 GHz ISM Band, a System Analysis

S. Haddadian, C. Scheytt, in: Electromagnetics Research Symposium, 2018

A complete system analysis for an integrated passive RFID transponder designed at 5.8 GHz range is presented, and a comprehensive set of design concerns for the rectifier circuit as the core of the harvesting block is also discussed. The system analysis is complemented by transistor-level design and simulation of harvesting circuits in a commercial 65 nm CMOS technology. A differential drive rectifier (DDR) has been selected as the most efficient harvesting topology for microwave frequency applications, which works at very low input power levels. The circuit was designed and simulated including chip layout parasitics and antenna matching circuitry. Considering the power budget of the tag chip, a power conversion efficiency of roughly 68.4% is achieved in simulation for an input RF power of around -11.26dBm.


SHF RFID System for Automatic Process Optimization with Intelligent Tools

P. Kuhn, S. Haddadian, F. Meyer, M. Hoffmann, A. Grabmaier, C. Scheytt, T. Kaiser, in: Smart SysTech 2017; European Conference on Smart Objects, Systems and Technologies, VDE ITG, 2017

In this paper we present theoretical, simulated and measured data for a reader to tag communication RFID system at 5.8 GHz. First a theoretical link budget analysis for a reader to tag architecture is shown for a wireless industrial application at 1m distance. This includes a power budget of the passively powered transponder. The received power level of the backscattered data for the theoretical link budget is -52:5 dBm. For the first setup slot antennas are developed and measured in the anechoic chamber. The measured gain is 4.0 dB. The power of the backscatter data in setup 1 is -74:8 dBm. This corresponds to the theoretical link budget since, all losses such as cable or lower antenna gain are taken into account. Setup 2 is upgraded on the reader side with horn antennas. At 5.8 GHz, the gain reaches the value of 10.8 dB. The second setup shows improvement in the receiving backscattered power to a value of -62:4 dBm. Furthermore, as a solution to detect those transponders not presented in the main slope of the antenna, a steerable beam is introduced by means of a Rotman lens. On the topic of the passive transponder, different harvesting topologies at 5.8 GHz are investigated, and the efficiency simulation of the harvesting circuitry has been performed. The simulated efficiency of the implemented technique is 68 %.

Energy Harvesting Analysis for Next Generation Passive RFID Tags

S. Haddadian, C. Scheytt, R. Kramer, in: ANALOG 2017; 16th ITG/GMM-Symposium, Technische Universität Berlin, 2017, pp. 18

This paper focuses on the design of a high efficiency cross-connected differential drive rectifier for next-generation passive RFID tags. To provide a realistic estimation of the transponders’power and efficiency requirements at 5.8 GHz, detailed link/power-budget analysis for various blocks of the tag chip is carried out. From link budget analysis realistic RF power levels are obtained and a rectifier with high conversion efficiency at low power levels is designed. Simulations based on a commercial 65nm CMOS technology investigate the suitability of the harvesting circuit for 5.8 GHz RFID tags.

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