Dr. Tobias Kenter

Mitglied - Postdoc

Mitglied - Postdoc
Mitglied - Postdoc
Fachberater FPGA Beschleunigung
Büro­anschrift:
Mersinweg 5
33100 Paderborn
Raum:
X1.119

Publikationen

Aktuelle Publikationen

Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL
M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, ArXiv:2403.18374 (2024).
Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures
K. Olgu, T. Kenter, J. Nunez-Yanez, S. Mcintosh-Smith, in: Proceedings of the 12th International Workshop on OpenCL and SYCL, ACM, 2024.
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks
M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (2023).
Compute Centers I: Heterogeneous Execution Environments
T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.
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